JPS60192540U - Electronic preset counter - Google Patents
Electronic preset counterInfo
- Publication number
- JPS60192540U JPS60192540U JP8032384U JP8032384U JPS60192540U JP S60192540 U JPS60192540 U JP S60192540U JP 8032384 U JP8032384 U JP 8032384U JP 8032384 U JP8032384 U JP 8032384U JP S60192540 U JPS60192540 U JP S60192540U
- Authority
- JP
- Japan
- Prior art keywords
- selection
- control input
- preset counter
- count
- clock
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Debugging And Monitoring (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案による電子式ブリセットカラン汐の機能
ブロック図、第２図ａはＲＡＭ９の記憶内容を示す図、
第２図すはその各ステップの内容を示すメモリマ゛イブ
であり、第５図は本実施例の電子式プリセットカウンタ
のフロントパネル面ヲ示す図、第４図はその動作を示す
フローチャートである。
１・・・・・・計数入力部、２・・・・・・計数／クロ
ック選択 、手段、３・・・・・・クロック発生部、
４・・・・・・入力カウンタ、５・・・・・・比較手段
、６・・・・・・制御回路、７・・・・・・比較レジス
タ、８・・・・・・ＲＯＭ、 ９・・・・・・ＲＡＭ、
１０・・・・・・プログラム入力部、１１・・・・・・
制御入力部、１２・・・・・・表示部、１３・・・・・
・出力回路、２０・・・・・・テンキー／タイマー人カ
キ−１２１・・・・・・デバッグキー、２４・・・・・
・出力表示部。FIG. 1 is a functional block diagram of the electronic brisset device according to the present invention, and FIG. 2a is a diagram showing the memory contents of the RAM 9.
FIG. 2 is a memory file showing the contents of each step, FIG. 5 is a front panel view of the electronic preset counter of this embodiment, and FIG. 4 is a flowchart showing its operation. 1...Counting input section, 2...Counting/clock selection, means, 3...Clock generation section,
4... Input counter, 5... Comparison means, 6... Control circuit, 7... Comparison register, 8... ROM, 9 ...RAM,
10...Program input section, 11...
Control input section, 12...Display section, 13...
・Output circuit, 20...Numeric keypad/timer key-121...Debug key, 24...
・Output display section.
Claims (2)
手段と、 制御対象から与えられる計数入力と前記クロック発生手
段のクロック信号を選択する選択手段と、 前記選択手段より与えられる計数値を計数する計数手段
と、 デンくラグモードの選択を含む制御入力手段と、 出力状態を表示する表示手段と、 前記記憶手段の一連のステップを順次読出すと共に読出
されたステップの計数設定値と計数手段の計数値とを比
較し、計数値の一致出力を与える比較手段と、 前記制御入力手段よりデバッグモードが選択されたとき
前記比較手段より得られた一致出力を前記表示手段に与
える制御手段と、を具備することを特徴とする電子式プ
リセットカウンタ。(1) Clock generation means that generates a clock signal of a constant period; selection means that selects a count input given from a controlled object and a clock signal of the clock generation means; and a counter that counts the count value given by the selection means. control input means including a selection of a digital lag mode; a display means for displaying an output state; and a count setting value of the read step and a count value of the counting means for sequentially reading out a series of steps of the storage means. and a control means for providing a matching output obtained from the comparing means to the display means when a debug mode is selected by the control input means. An electronic preset counter characterized by:
の計数速度を選択する選択手段を含むものであることを
特徴とする実用新案登録請求の範囲第１項記載の電子式
プリセットカウンタ。(2) The electronic preset counter according to claim 1, wherein the control input means includes selection means for selecting the counting speed of the internal clock during debugging.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8032384U JPS60192540U (en) | 1984-05-29 | 1984-05-29 | Electronic preset counter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8032384U JPS60192540U (en) | 1984-05-29 | 1984-05-29 | Electronic preset counter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60192540U true JPS60192540U (en) | 1985-12-20 |
Family
ID=30626063
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8032384U Pending JPS60192540U (en) | 1984-05-29 | 1984-05-29 | Electronic preset counter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60192540U (en) |
-
1984
- 1984-05-29 JP JP8032384U patent/JPS60192540U/en active Pending
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