JPS60192351A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS60192351A
JPS60192351A JP59047580A JP4758084A JPS60192351A JP S60192351 A JPS60192351 A JP S60192351A JP 59047580 A JP59047580 A JP 59047580A JP 4758084 A JP4758084 A JP 4758084A JP S60192351 A JPS60192351 A JP S60192351A
Authority
JP
Japan
Prior art keywords
film
thin
bonding
films
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59047580A
Other languages
Japanese (ja)
Inventor
Kazuo Matsuzaki
松崎 一夫
Misao Saga
佐賀 操
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Corporate Research and Development Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Corporate Research and Development Ltd filed Critical Fuji Electric Corporate Research and Development Ltd
Priority to JP59047580A priority Critical patent/JPS60192351A/en
Publication of JPS60192351A publication Critical patent/JPS60192351A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01022Titanium [Ti]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1203Rectifying Diode
    • H01L2924/12032Schottky diode

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To provide laminated thin films with high bonding strength by a method wherein an Si evaporation film as an intermediate layer is laid between thin films to be diffused mutually therewith. CONSTITUTION:Ti 4, Cu 5 and Ni 8 to be base metals are respectively laminated as the first, second and third layers to join these thin film layers. The films Ti 4 and Cu 5 are interfacially junctioned at relatively low junction strength by means of laying an Si evaporation film 13 between the interface thereof. The active Si evaporation film 13 may be diffused mutually with the Ti 4 and Cu 5 at relatively low temperature of around 400 deg.C to form a silicide easily providing said films Ti 4 and Cu 5 with solid bonding. The Si evaporation film 13 provided with sufficiently thin thickness no exceeding 0.1mum may easily make a junction electrically ohmic. The characteristics of a semiconductor element may not be deteriorated since only an extremely thin Si film is added thereto.

Description

【発明の詳細な説明】 〔発明の属する技術分野〕 本発明は半導体素子に設けられる金属、絶縁膜などの薄
膜を相互に積層する方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field to which the Invention Pertains] The present invention relates to a method for laminating thin films such as metal and insulating films provided on a semiconductor device.

〔従来技術とその問題点〕[Prior art and its problems]

例えば多層電極構造を有するフリップチップ、バリヤメ
タルと絶縁膜との積層構造をもったショットキダイオー
ドのような半導体素子においては。
For example, in semiconductor devices such as flip chips having a multilayer electrode structure and Schottky diodes having a laminated structure of a barrier metal and an insulating film.

金属同志、絶縁膜同志もしくは金属と絶縁膜の間で薄膜
相互の接合が行われ、これらが強固に接合されることが
望ましい。
It is desirable that thin film-to-thin film bonding is performed between metals, insulating films, or metals and insulating films, and these are strongly bonded.

一般にこれら薄膜の接合には大別して界面接合、相互拡
散接合および中間層接合の三つの接合形態が知られてい
る。
In general, three types of bonding are known for bonding these thin films: interface bonding, interdiffusion bonding, and intermediate layer bonding.

界面接合は互に接している二つの物質量に働く分子間お
よび原子間相互作用、すなわち静電的またはVan d
er Waals的な相互作用であって接合強度は主と
して接合時の両物質の界面状態に依存する。したがって
界面接合により薄膜相互の接合強度を向上させるために
は、被接合面の表面処理やこの面に形成される薄膜の生
成時の写囲気、真空度などに細心の注意を払い、最適条
件で行われねばならないが、通常の抵抗加熱や電子ビー
ム加熱によシ蒸着される薄膜を形成する場合には蒸着面
の良好な状態が再現されに<<1表面状態の制御が困難
であるという問題がある。蒸着にかわる手法として知ら
れているものはスパッタリングであり、この場合はスパ
ッタ薄膜形成前のスバツタクリーニングにより表面処理
されて、スパッタされた原子の運動エネルギーのために
接合性が向上するという利点があるので界面接合に対し
て有効な薄膜形成方法であるが、被接合側の下地にスパ
ッタダメージを与えるという問題がある。したがって薄
膜を蒸着やスパッタリングによって形成するとともに被
接着膜に薄膜を界面接合するだけでは十分な接合強度が
得られず、半導体素子の信頼性に欠ける。
Interfacial bonding involves intermolecular and atomic interactions that occur between two amounts of substances that are in contact with each other, i.e., electrostatic or Van d
This is an er Waals-like interaction, and the bonding strength mainly depends on the state of the interface between the two materials at the time of bonding. Therefore, in order to improve the bonding strength between thin films through interfacial bonding, careful attention must be paid to the surface treatment of the surfaces to be bonded, the atmosphere and degree of vacuum during the formation of the thin film formed on these surfaces, and the optimum conditions are required. However, when forming a thin film deposited by ordinary resistance heating or electron beam heating, it is difficult to reproduce the good condition of the deposition surface and the problem is that it is difficult to control the surface condition. There is. A known alternative to vapor deposition is sputtering, in which the surface is treated by sputter cleaning before sputtered thin film formation, which has the advantage of improving bonding properties due to the kinetic energy of the sputtered atoms. Although this method is effective for forming a thin film for interfacial bonding, it has the problem of sputtering damage to the base on the side to be bonded. Therefore, by simply forming a thin film by vapor deposition or sputtering and bonding the thin film to a film to be bonded at an interface, sufficient bonding strength cannot be obtained, resulting in a lack of reliability of the semiconductor element.

相互拡散接合は界面接合した金属同志の薄膜をさらに高
温に加熱して接合界面で薄膜間に相互拡散を起こさせ、
この相互拡散によって形成された合金層の金属結合によ
るものであって、界面接合のままより接合強度は高いが
接合強度はこの合金層自体の強さが問題とガるから、相
互拡散を起こしやすい構成金属が選ばれねばならないこ
とと、高温処理が不可能々プロセスを含む素子には適用
できないという制約を受ける。
Interdiffusion bonding involves heating thin films of interfacially bonded metals to a higher temperature to cause interdiffusion between the thin films at the bonding interface.
This is due to the metallic bonding of the alloy layer formed by this interdiffusion, and although the bonding strength is higher than that of interface bonding, the problem with the bonding strength is the strength of the alloy layer itself, so interdiffusion is likely to occur. Constituent metals must be selected, and high-temperature processing is not applicable to devices that involve processes that are impossible.

中間層接合は例えばAt、!:5i02などの薄膜の接
合のように、両薄膜の間にはA L x Osからなる
中間層が形成され、この中間層はAt膜とS i O,
膜とを共有して結合するので、高い強度を有する接合が
得られ、酸化されやすい金属同志や酸化されやすい金属
と酸化膜とを組合わせて接合させるときには有効である
。しかしこの場合も酸化されやすい金属に対してのみ効
果的な接合が得られるものであって、いかなる薄膜にも
成り立つわけではない。
For example, the intermediate layer junction is At,! :5i02 and other thin films, an intermediate layer made of A L x Os is formed between the two thin films, and this intermediate layer is made of At film and S i O,
Since the bond is shared with the film, a bond with high strength can be obtained, and it is effective when bonding metals that are easily oxidized or metals that are easily oxidized and an oxide film. However, in this case as well, effective bonding can only be achieved with metals that are easily oxidized, and cannot be achieved with any thin film.

例えば第1図A−Eは従来よく知られているフリップチ
ップの突起電極形成過程を示した断面図である。
For example, FIGS. 1A-1E are cross-sectional views showing the process of forming protruding electrodes of a conventionally well-known flip chip.

第1図ではSt基板10表面に設けられた厚さ1μmの
At配線2の上に厚さ1μmのS i 02など表面保
護膜3を形成し、窓明けする工程A、窓明けされたコン
タクトホール部に第1層目の下地金属例えば厚さ0.5
μmのTi膜4と第2層目の下地金属例えば厚さ1μm
のCu膜5を被着する工程B、はんだ領域形成のために
フォトレジスト6を塗布して不要部を除去する工程C、
フォトレジスト6を除去してはんだ領域以外の部分を再
び7オトレジスト7を塗布する工程D、第3層目の下地
金属Nlめっき8を施し、例えばPb−an系はんだ合
金めっきを行ってレジスト7を除去した後、はんだめっ
き層をリフローして突起電極9とする工程Eとに大別し
て示した。
FIG. 1 shows a step A in which a surface protection film 3 such as Si02 with a thickness of 1 μm is formed on the At wiring 2 with a thickness of 1 μm provided on the surface of the St substrate 10, and a window is opened. For example, the thickness of the base metal of the first layer is 0.5
μm thick Ti film 4 and second layer base metal, for example, 1 μm thick
Step B of depositing a Cu film 5, Step C of applying a photoresist 6 to form a solder region and removing unnecessary parts,
Step D of removing the photoresist 6 and applying the photoresist 7 again to areas other than the solder area, applying a third layer of base metal Nl plating 8, performing, for example, Pb-an based solder alloy plating, and removing the resist 7. After that, the solder plating layer is reflowed to form the protruding electrode 9, which is roughly divided into process E.

かくして得られたフリップチップのコンタクトホール部
に形成された半球状のはんだ突起電極9には下地金属と
して第1層KTi4、第2層にCu5、第3層にNi 
8が積層されて、それぞれの薄膜層が接合されることに
なる。この場合、配線金属のA42とTi4.および5
in2の表面保護膜3とTi 4との接合界面はいずれ
も中間層が形成されて中間層接合となり、またCu 5
とNi 8、およびNi 13とはんだ9との接合界面
は相互拡散接合となり、これら薄膜積層体の中では比較
的高い接合強度を有するが Tp + 4とC【15の
間は単に界面接合であるから比較的低い接合強度しか得
られない。したがってこのような薄膜積層構造を有する
フリップチップの突起はんだ電極は下地金属のT14と
Cu 5の界面で剥離を生ずるという 5− 欠点をもっている。
The hemispherical solder protrusion electrode 9 formed in the contact hole portion of the flip chip thus obtained has a first layer of KTi4, a second layer of Cu5, and a third layer of Ni as base metals.
8 are stacked and the respective thin film layers are bonded. In this case, the wiring metals A42 and Ti4. and 5
An intermediate layer is formed at the bonding interface between the surface protective film 3 of in2 and Ti 4 to form an intermediate layer bond, and Cu 5
The bonding interfaces between and Ni 8, and Ni 13 and solder 9 are mutual diffusion bonding, and have a relatively high bonding strength among these thin film laminates, but the bonding between Tp + 4 and C[15 is simply an interfacial bonding. Only relatively low bonding strength can be obtained. Therefore, the protruding solder electrode of a flip chip having such a thin film laminated structure has the disadvantage that peeling occurs at the interface between the underlying metal T14 and Cu5.

〔発明の目的〕[Purpose of the invention]

本発明の目的は上述の欠点を除去し、薄膜相互の界面特
性に影響されず、いかなる材料の薄膜の接合にも適用す
ることができ、接合強度が高く、しかも半導体素子の特
性になんらの悪影響を及ぼすことのない薄膜の積層方法
を提供するものである。
The purpose of the present invention is to eliminate the above-mentioned drawbacks, be able to be applied to bonding thin films of any material without being affected by the interfacial characteristics between the thin films, and have high bonding strength without causing any adverse effects on the characteristics of semiconductor devices. The purpose of the present invention is to provide a method for laminating thin films without causing any adverse effects.

[発明の要点] 本発明は半導体素子に設けられる金属や酸化膜などの薄
膜を積層するに際して、薄膜層間に極薄の81蒸着膜を
介在させて相互拡散や中間層の形成により積層薄膜に高
い接合強度を付与させるものである。
[Summary of the Invention] When laminating thin films such as metal or oxide films provided in a semiconductor element, the present invention interposes an extremely thin 81 vapor deposited film between the thin film layers to increase the thickness of the laminated thin film by interdiffusion and forming an intermediate layer. This provides bonding strength.

〔発明の実施例〕[Embodiments of the invention]

以下本発明を実施例に基づき説明する。 The present invention will be explained below based on examples.

第2図A−Eは第1図に示したのと同様のフリップチッ
プの突起電極形成過程に本発明の方法を適用した場合で
あり、第1図と共通部分は同一符号で表わしである。第
2図A−Hの各工程は第16− 図の場合と互に対応しているので、その方法、手順の説
明は省略するが、第3図において本発明が適用され第1
図と異る工程は第2図Bの第1層目の下地金属Ti 4
と第2層目の下地金属5との間に厚さ0.05μm程度
のSi蒸着膜13を介在させるようにしていることであ
る。
2A to 2E show the case where the method of the present invention is applied to the process of forming protruding electrodes of a flip chip similar to that shown in FIG. 1, and parts common to those in FIG. 1 are represented by the same reference numerals. The steps in FIG. 2A-H correspond to those in FIG.
The process different from the one shown in the figure is the base metal Ti 4 of the first layer in Figure 2B.
A Si vapor deposited film 13 having a thickness of approximately 0.05 μm is interposed between the base metal 5 of the second layer and the base metal 5 of the second layer.

第1図で説明したようにTi膜4とCu膜5とはこのま
まではTi 4の蒸着面にCu 5が付着して々る界面
接合であって接合強度が低いのでこれらの界面にSi蒸
着膜を介在させると、Si蒸着膜は単結晶SIと異り活
性であるから、比較的低温の400℃程度でもTi 4
やCu 5と相互拡散してこれらの化合物シリサイドを
つくりやすく、とのシリサイド層の形成によりTi膜4
とCu膜5の強固々接合が得られる。この場合Si蒸着
膜13の厚さを十分薄くすることによシミ気的にオーミ
ックな接合が容易に得られ、Si蒸着膜13は0.1μ
m以下の厚さとするのがよい。
As explained in FIG. 1, the Ti film 4 and Cu film 5 are bonded at an interface where Cu 5 is attached to the evaporated surface of Ti 4, and the bonding strength is low, so a Si evaporated film is attached to these interfaces. Since the Si vapor deposited film is active unlike single-crystal Si, Ti 4
These compounds easily form silicide by interdiffusion with and Cu 5, and the formation of a silicide layer with Ti film 4
A strong bond between the film and the Cu film 5 can be obtained. In this case, by making the thickness of the Si vapor deposited film 13 sufficiently thin, a spot-like ohmic bond can be easily obtained.
It is preferable that the thickness be less than m.

第3図はショットキパリアダづオードの部分的断面図を
示したものであり本発明の方法を適用した場合である。
FIG. 3 shows a partial cross-sectional view of a Schottky pad, in which the method of the present invention is applied.

第3図において81基板1oに設けられるバリアメタル
11はSi酸化膜12の上を一部覆うようにオーバーオ
キサイド部を形成することが多い。しかしバリアメタル
はこのショットキバリアダイオードの特性に応じて各種
の金属が用いられるので、例えばバリアメタルにMOな
どを使用した場合、MOと81酸化膜との接合面は十分
高い強度が得られないことがある。したがってこの場合
バリアメタル11とSt酸化W12との間、に第3図の
ように8層蒸着膜14を1層設ける。すなわちMO膜1
1とSi酸化膜12のみでは強固な接合が得られないの
に対してSi蒸着膜14を介在させてMO膜11との界
面でMOシリサイドを形成し、Si酸化膜12との界面
では酸素を共有した中間層を形成することにより十分な
接合強度を得るようにしたものである。
In FIG. 3, the barrier metal 11 provided on the substrate 1o 81 often forms an overoxide portion so as to partially cover the top of the Si oxide film 12. In FIG. However, various metals are used as the barrier metal depending on the characteristics of this Schottky barrier diode, so if MO is used as the barrier metal, the bonding surface between the MO and the 81 oxide film may not have sufficiently high strength. There is. Therefore, in this case, one eight-layer vapor deposited film 14 is provided between the barrier metal 11 and the St oxide W 12 as shown in FIG. That is, MO film 1
1 and the Si oxide film 12 alone, a strong bond cannot be obtained by interposing the Si vapor deposited film 14 to form MO silicide at the interface with the MO film 11 and oxygen at the interface with the Si oxide film 12. Sufficient bonding strength is obtained by forming a shared intermediate layer.

〔発明の効果〕〔Effect of the invention〕

以上実施例で説明したように半導体素子に各種薄膜を積
層接合するに当、す、互に拡散しにくい薄膜同志の組み
合わせで十分な接合強度が得られないときでも、この薄
膜の間に極薄のSi膜を1層介在させることにより、拡
散層や中間層を形成して接合強度を高めることができる
ので半導体素子の積層薄膜における剥離現象を起こすと
とが々くなる。しか屯薄膜の種類を選ぶことなく金属、
酸化物などのいずれの薄膜との組み合わせであってもよ
く、これらをSi薄膜を挟んで接合することは比較的低
温で、容易に行うことができ、極薄の81膜が付加され
るだけであるから、半導体素子の特性は全く損われるこ
とがないなどの利点がある。
As explained in the examples above, when laminating and bonding various thin films to semiconductor devices, even if sufficient bonding strength cannot be obtained by combining thin films that do not easily diffuse into each other, it is possible to By interposing one layer of Si film, it is possible to form a diffusion layer or an intermediate layer and increase the bonding strength. Therefore, if a peeling phenomenon occurs in the laminated thin film of a semiconductor element, it will be a problem. Metal, regardless of the type of thin film.
It can be combined with any thin film such as oxide, and bonding these with a Si thin film in between can be easily done at a relatively low temperature, and only requires adding an extremely thin 81 film. This has the advantage that the characteristics of the semiconductor element are not impaired at all.

【図面の簡単な説明】[Brief explanation of the drawing]

算1図は従来のフリップチップの突起電極工程図、第2
図は本発明の方法を適用したフリップチップの突起電極
工程図、第3図は本発明の方法を適用しまたショットキ
ダイオードの部分断面図である。 1.10・・・シリコン基板、3.12・・・酸化膜、
4・・・Ti膜、5・・・Cu膜、8・・・Nrめっき
、9・・・第1図
Figure 1 is a process diagram of the protruding electrode of a conventional flip chip;
The figure is a process diagram of a protruding electrode of a flip chip to which the method of the present invention is applied, and FIG. 3 is a partial sectional view of a Schottky diode to which the method of the present invention is applied. 1.10... Silicon substrate, 3.12... Oxide film,
4...Ti film, 5...Cu film, 8...Nr plating, 9...Figure 1

Claims (1)

【特許請求の範囲】 1)半導体基板の表面の所定の領域に導電性、半導電性
または絶縁性の薄膜を積層して電極、配線または表面保
護膜を形成するに際し、積層される薄膜の少くとも一つ
の上にシリコンの薄膜を形成しその上に次の薄膜を重ね
ることを特徴とする半導体装置の製造方法。 2、特許請求の範囲第1項記載の方法において、シリコ
ンの薄膜の厚さが0.1μm以下であることを特徴とす
る半導体装置の製造方法。
[Claims] 1) When forming electrodes, wiring, or a surface protective film by laminating conductive, semiconductive, or insulating thin films on a predetermined region of the surface of a semiconductor substrate, a small number of thin films to be laminated A method of manufacturing a semiconductor device characterized by forming a thin film of silicon on one layer and then layering the next thin layer on top of that. 2. A method for manufacturing a semiconductor device according to claim 1, wherein the thickness of the silicon thin film is 0.1 μm or less.
JP59047580A 1984-03-13 1984-03-13 Manufacture of semiconductor device Pending JPS60192351A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59047580A JPS60192351A (en) 1984-03-13 1984-03-13 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59047580A JPS60192351A (en) 1984-03-13 1984-03-13 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS60192351A true JPS60192351A (en) 1985-09-30

Family

ID=12779185

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59047580A Pending JPS60192351A (en) 1984-03-13 1984-03-13 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS60192351A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52116075A (en) * 1976-03-26 1977-09-29 Hitachi Ltd Preparation of film for protecting surface of electronic parts

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52116075A (en) * 1976-03-26 1977-09-29 Hitachi Ltd Preparation of film for protecting surface of electronic parts

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