JPS60190045A - Supervisory system of ciphering synchronization - Google Patents
Supervisory system of ciphering synchronizationInfo
- Publication number
- JPS60190045A JPS60190045A JP59047360A JP4736084A JPS60190045A JP S60190045 A JPS60190045 A JP S60190045A JP 59047360 A JP59047360 A JP 59047360A JP 4736084 A JP4736084 A JP 4736084A JP S60190045 A JPS60190045 A JP S60190045A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- frame synchronization
- circuit
- pattern
- frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/12—Transmitting and receiving encryption devices synchronised or initially set up in a particular manner
Landscapes
- Engineering & Computer Science (AREA)
- Computer Security & Cryptography (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
Description
【発明の詳細な説明】
ｆａ） 発明の技術分野
本発明は秘匿伝送システムの秘匿同期を監視する秘匿同
期監視方式の改良に関するものである。DETAILED DESCRIPTION OF THE INVENTION fa) Technical Field of the Invention The present invention relates to an improvement of a secure synchronization monitoring method for monitoring secure synchronization of a secure transmission system.
（ｂｌ 従来技術と問題点
データ伝送方式における各端末装置間のデータ信号を秘
匿して伝送する秘匿伝送システムは第１図に示すような
ブロック図よりなっている。(bl) Prior Art and Problems A secure transmission system for secretly transmitting data signals between terminal devices in a data transmission system has a block diagram as shown in FIG.
すなわち、第１図の秘匿伝送システムのブロック図に示
すように、秘匿伝送システムは、伝送信号を構成するフ
レーム同期信号と該同期信号に同期したデータ信号を出
力する端末装置１と、端末袋Ｗ１より出力されたフレー
ム同期信号を含むデータ信号を所定のＷｊ匿倍信号変換
し、出力する秘匿変換部２と、秘匿変換部２より出力さ
れた秘匿信号を伝送装置３．線路４．伝送装置３１を介
して受信し、秘匿信号を伝送信号に復調し、他の端末装
置１１に出力する秘匿復調部２１とより構成されており
、それぞれの端末装置間で相互に秘匿信号を伝送する機
能を持っている。That is, as shown in the block diagram of the secure transmission system in FIG. 1, the secure transmission system includes a terminal device 1 that outputs a frame synchronization signal constituting a transmission signal and a data signal synchronized with the synchronization signal, and a terminal bag W1. The data signal including the frame synchronization signal output from the cipher converter 2 converts the data signal including the frame synchronization signal into a predetermined Wj concealment signal and outputs the converted signal, and the cipher signal outputted from the cipher converter 2 is transmitted to the transmission device 3. Railway line 4. It is composed of a secrecy demodulation unit 21 that receives the secrecy signal via the transmission device 31, demodulates the secrecy signal into a transmission signal, and outputs it to other terminal devices 11, and mutually transmits the secrecy signal between the respective terminal devices. It has a function.
この秘匿信号伝送方式において、従来の秘匿同期の監視
には、秘匿信号の信号列の中に監視用のビットを挿入し
、受信側の秘匿復調部２１で前記監祝用ビットを検出し
て秘匿同期を監視する方式と、第２図の他の同期監視回
路のブロック図に示すように、端末装置１１に内蔵され
た同期手段５によりデータ信号の同期を検出し、その検
出結果で同期がずれていると判断すると補正信号Ｙを秘
匿変換復調部２１に出力し、再同期をかけるようにする
方式とがある。前者の方式は監視用ビット数が増加する
こととなり、それがため伝送速度が増加し、伝送品質が
相対的に低下するといった欠点がある。In this secret signal transmission system, conventional secret synchronization monitoring involves inserting a monitoring bit into the signal sequence of the secret signal, detecting the monitoring bit in the receiving side's encryption demodulation section 21, and encrypting the secret synchronization. As shown in the method for monitoring synchronization and the block diagram of another synchronization monitoring circuit in FIG. There is a method in which when it is determined that the correction signal Y is detected, the correction signal Y is output to the secret conversion demodulation section 21 and resynchronization is performed. The former method has the disadvantage that the number of monitoring bits increases, which increases the transmission speed and relatively lowers the transmission quality.
また、後者は秘匿同期を監視するための同期手段を備え
た端末装置が必要となり、端末装置を除いた秘匿伝送路
の試験ができないこと、および端末装置を除いた秘匿の
中継伝送路の構成がとれないといった欠点がある。In addition, the latter requires a terminal device equipped with synchronization means to monitor secure synchronization, making it impossible to test the secure transmission path excluding the terminal device, and the configuration of the confidential relay transmission path excluding the terminal device. There is a drawback that it cannot be removed.
（Ｃ１発明の目的
本発明は上述した従来の欠点に鑑み創案されたもので、
その目的は端末装置のフレーム同期信号が得られなくて
も、フレーム同期信号と同等の信号にて、秘匿装置自体
で秘匿同期の監視ができる秘匿同期監視方式を提供する
ことにある。(C1 Purpose of the Invention The present invention was devised in view of the above-mentioned conventional drawbacks,
The purpose is to provide a secure synchronization monitoring method that allows the secure synchronization to be monitored by the secure device itself using a signal equivalent to the frame synchronization signal even if the frame synchronization signal of the terminal device cannot be obtained.
（ｄｌ 発明の構成
そしてこの目的は本発明によれば、複数の端末装置に対
応して秘匿装置を設け、該秘匿装置には端末装置より出
力されるフレーム同期信号を含む伝送信号を秘匿信号に
変換する変換部と、受信した秘匿信号の解読を行う復調
部を備え、かつ前記端末装置には受信フレーム同期信号
の同期手段を備えてなり、さらに前記秘匿装置の変換部
に前記フレーム同期信号と同じ信号を発生ずる信号発生
回路と、該信号発生回路の出力信号と前記フレーム同期
信号の両信号の時間差を調整する位相調整回路と、前記
復調部に前記両信号の同期をとる同期回路とをｆ１設し
、前記両フレーム同期信号のそれぞれにて秘匿同期の監
視ができることを特徴とする秘匿同期の監視方式により
達せられる。According to the present invention, a concealing device is provided corresponding to a plurality of terminal devices, and the concealing device converts a transmission signal including a frame synchronization signal outputted from the terminal device into a concealed signal. The terminal device includes a converting unit for converting the data, and a demodulating unit for decoding the received secret signal, and the terminal device includes synchronization means for synchronizing the received frame synchronization signal, and the converting unit of the secret device includes a synchronization unit for synchronizing the received frame synchronization signal. A signal generation circuit that generates the same signal, a phase adjustment circuit that adjusts the time difference between the output signal of the signal generation circuit and the frame synchronization signal, and a synchronization circuit that synchronizes the two signals in the demodulation section. This is achieved by a secure synchronization monitoring method, which is characterized in that it is possible to monitor secure synchronization using each of the two frame synchronization signals.
ｔａ＋ 発明の実施例
以下、添付図面により本発明の一実施例を説明する。第
３図は本発明の一実施例を説明するためのブロック図で
あり、第１図と同一符号は同一部位を示している。ta+ Embodiment of the Invention Hereinafter, an embodiment of the present invention will be described with reference to the accompanying drawings. FIG. 3 is a block diagram for explaining one embodiment of the present invention, and the same reference numerals as in FIG. 1 indicate the same parts.
すなわち、実施例の秘匿同期の監視方式は第３図に示す
ように、秘匿変換部２に端末装置１より出力されるフレ
ーム同期信号と同じフレーム同期信号を出力するフレー
ムパターン発生回路７と、前記フレーム同期信号と前記
伝送フレーム同期信号との時間位置を調整する位相調整
回路６とを備え、また秘匿ｆｕ １ｌｉ１部２１には秘
匿同期を監視するフレーム同期回路８が付加されている
。That is, as shown in FIG. 3, the security synchronization monitoring system of the embodiment includes a frame pattern generation circuit 7 that outputs the same frame synchronization signal as the frame synchronization signal output from the terminal device 1 to the security converter 2, and the It is provided with a phase adjustment circuit 6 that adjusts the time position of the frame synchronization signal and the transmission frame synchronization signal, and a frame synchronization circuit 8 that monitors the security synchronization is added to the security fu 1li1 section 21.
まづ位相調整回路６の動作を第４図に示す位相ＪｊｉＩ
整回路のブロック図と、第５図のパターン信号列図とに
より説明する。すなわち、第４図において、秘匿変換部
２に付加されたフレームパターン発生回路７は伝送フレ
ーム同期信号のパターンＡと同等のフレー同期信号であ
るフレーム同期パターンＢを発佳し、スイッチ回路６５
と位相比較部６３とに出力する。いま、端末装置１より
伝送フレーム同期パターンへが入力されない時、つまり
、端末装置１と秘匿変換部２とが接続されていない場合
は、入力信号検出回路６１が信号断を検出しスイッチ回
路６５を駆動してフレーム同期パター７８ｔ−搬送装置
３に出力する。First, the operation of the phase adjustment circuit 6 is shown in FIG.
This will be explained using a block diagram of the adjustment circuit and a pattern signal sequence diagram in FIG. That is, in FIG. 4, the frame pattern generation circuit 7 added to the security converter 2 generates a frame synchronization pattern B which is a frame synchronization signal equivalent to the transmission frame synchronization signal pattern A, and the switch circuit 65
and is output to the phase comparator 63. Now, when the transmission frame synchronization pattern is not input from the terminal device 1, that is, when the terminal device 1 and the security converter 2 are not connected, the input signal detection circuit 61 detects a signal disconnection and switches the switch circuit 65. It is driven and output to the frame synchronized putter 78t-conveying device 3.
一方、端末装置１と秘匿変換部２とが接続されている場
合は、第５図のＡに示す伝送フレーム同期パターンへの
信号列はフレーム同期回路６２に入力される。この際、
フレーム同期回路６２は入力された伝送フレーム同期パ
ターンＡのフレーム同期信号を検出し、位相比較部６３
に出力する。位相比較部６３は前記伝送フレーム同期信
号と前記フレームバター ７９ ／ＩＥ回路７より入力
したフレームパターン信号Ｂのフレーム同期信号との位
相を比較し、位相差値を検出し、その差値に対応した差
値信号をメモリ回路６４に出力する。この差値信号によ
りメモリ回路６４は制御され、フレーム同期回路６２が
らメモリ回路６４に直接読込まれている伝送フレーム同
期パターンＡの同期信号位相位置＾１をフレーム同期パ
ターン信号Ｂの同期信号位相位置Ｂ１に合わせた伝送フ
レーム同期パターンＣを読出させ、スイッチ回路６５に
出力する。スイッチ回路６５は入力信号検出回路６エの
制御により、伝送フレーム同期パターンへの入力時は伝
送フレーム同期バターンＣを搬送装置３に出力する。On the other hand, when the terminal device 1 and the security converter 2 are connected, the signal train for the transmission frame synchronization pattern shown in A in FIG. 5 is input to the frame synchronization circuit 62. On this occasion,
The frame synchronization circuit 62 detects the frame synchronization signal of the input transmission frame synchronization pattern A, and the phase comparator 63 detects the frame synchronization signal of the input transmission frame synchronization pattern A.
Output to. The phase comparator 63 compares the phases of the transmission frame synchronization signal and the frame synchronization signal of the frame pattern signal B input from the frame butter 79/IE circuit 7, detects a phase difference value, and detects a phase difference value. The difference value signal is output to the memory circuit 64. The memory circuit 64 is controlled by this difference value signal, and the frame synchronization circuit 62 changes the synchronization signal phase position ^1 of the transmission frame synchronization pattern A, which is directly read into the memory circuit 64, to the synchronization signal phase position B1 of the frame synchronization pattern signal B. The transmission frame synchronization pattern C corresponding to the transmission frame synchronization pattern C is read out and output to the switch circuit 65. Under the control of the input signal detection circuit 6e, the switch circuit 65 outputs the transmission frame synchronization pattern C to the transport device 3 when the transmission frame synchronization pattern is input.
以上の結果、端末装置間接続されていない時でも秘匿同
期が確立できることはもとより、端末装置間で秘匿信号
の伝送が行われる時は端末装置が発生している伝送フレ
ーム同期信号とフレームパターン発ＩＪニ回路が発生し
たフレーム同期信号との時間位置のずれが無（なり、伝
送信号の受信ができなくなったり、データビットの消失
が起ることを防止できる。As a result of the above, not only can secure synchronization be established even when the terminal devices are not connected, but also when transmitting a secure signal between terminal devices, the transmission frame synchronization signal generated by the terminal device and the frame pattern generation IJ There is no time position shift with the frame synchronization signal generated by the two circuits, and it is possible to prevent transmission signals from being unable to be received and data bits from being lost.
このように、本発明によれば、端末装置の有無にかかわ
らず、伝送フレームパターンが秘匿変換部２にて伝送フ
レームパターンと同等のフレームパターンが付与できる
為、第３図に示すように秘匿復調部２１にフレーム同期
回路８を設けておけば、秘匿変換部２と秘匿復調部２１
よりなる秘匿装置自体でフレーム同期の監視ができ、秘
匿の同期はずれ検出や再同期が伝送路速度を大にせず秘
匿装置自体で可能となる。As described above, according to the present invention, regardless of the presence or absence of a terminal device, the transmission frame pattern can be given a frame pattern equivalent to the transmission frame pattern in the encryption converter 2, so that the encryption demodulation can be performed as shown in FIG. If the frame synchronization circuit 8 is provided in the section 21, the encryption conversion section 2 and the encryption demodulation section 21
Frame synchronization can be monitored by the concealing device itself, and detection of loss of concealment synchronization and resynchronization can be performed by the concealing device itself without increasing the transmission path speed.
また、他の実施例として、第６図の端末装置の接続され
ない伝送路秘匿を行う２つの回線のブロック図に示すよ
うに、例えば、端末装置が無く、交換機９により２つの
回路が接続された場合にあっても、前述したように秘匿
変換部と秘匿復調部間にて、各々の回線において秘匿同
期の監視ができるため、各回線におりる障害を相手回線
にまで影響を与えることな（各々の回線で独立して復旧
することができる。In addition, as another example, as shown in the block diagram of two lines for concealing the transmission path in which the terminal equipment is not connected, as shown in the block diagram of FIG. Even in such a case, as mentioned above, the security synchronization can be monitored on each line between the security converter and the security demodulator, so that failures on each line will not affect the other line ( Each line can be restored independently.
（ｆｌ 名案の効果
以上の説明から明らかなように要するに本発明は、秘匿
変換部にフレームパターン発生回路吉位相調整回路と、
秘匿復調部にフレーム同期回路とを付加しすることによ
り、端末装置の有無にかかわらず秘匿同期の監視が伝送
路速度を大にすることなくできるといった効果がある。(fl Effect of the Good Idea As is clear from the above explanation, in short, the present invention includes a frame pattern generation circuit, a good phase adjustment circuit, and a frame pattern generation circuit in the secret conversion section.
By adding a frame synchronization circuit to the security demodulation section, there is an effect that security synchronization can be monitored without increasing the transmission path speed regardless of the presence or absence of a terminal device.
第１図は従来の秘匿伝送システムのブロック図、第２図
は他の秘匿回路のブロック図、第３図は本発明による一
実施例の秘匿伝送システムのブロック図、第４図は位相
調整回路のブロック図、第５図はパターン信号列図、第
６図は他の実施例の秘匿伝送システムのブロック図であ
る。
図において、１．１１は端末装置、２は秘匿変換部、３
，３１ば伝送装置、４．４１は線路、５は同期手段、６
，６６は位相調整回路、７，７Ｉはフレームパターン発
生回路、８，８１はフレーム同期回路、９は交換機、２
１は秘匿復調部、６１は入力信号断検出回路、６２ばフ
レーム同期回路、６３は位相比較部、６４はメモリ回路
、６５はスイッチ回路をそれぞれ示している。
第１図
１
第２図
第３図FIG. 1 is a block diagram of a conventional secure transmission system, FIG. 2 is a block diagram of another secure circuit, FIG. 3 is a block diagram of a secure transmission system according to an embodiment of the present invention, and FIG. 4 is a phase adjustment circuit. FIG. 5 is a pattern signal sequence diagram, and FIG. 6 is a block diagram of a secure transmission system according to another embodiment. In the figure, 1.11 is a terminal device, 2 is a security conversion unit, and 3
, 31 is a transmission device, 4.41 is a line, 5 is a synchronization means, 6
, 66 are phase adjustment circuits, 7 and 7I are frame pattern generation circuits, 8 and 81 are frame synchronization circuits, 9 is a switching device, 2
Reference numeral 1 indicates a secret demodulation section, 61 an input signal disconnection detection circuit, 62 a frame synchronization circuit, 63 a phase comparison section, 64 a memory circuit, and 65 a switch circuit. Figure 1 Figure 2 Figure 3
Claims (1)
には端末装置より出力されるフレーム同期信号を含む伝
送信号を秘匿信号に変換する変換部と、受信した秘匿信
号の解読を行う復調部を備え、かつ前記端末装置には受
信フレーム同期信号の同期手段を備えてなり、さらに前
記秘匿装置の変換部に前記フレーム同期信号と同じ信号
を発生する信号発生回路と、該信号発生回路の出力信号
と前記フレーム同期信号の両信号の時間差を調整する位
相調整回路と、前記復調部に前記両信号の同期をとる同
期回路とを付設し、前記両フレーム同期信号のそれぞれ
にて秘匿同期の監視ができることを特徴とする秘匿同期
の監視方式。A concealment device is provided corresponding to a plurality of terminal devices, and the concealment device includes a conversion unit that converts a transmission signal including a frame synchronization signal outputted from the terminal device into a secret signal, and a demodulation unit that decodes the received secret signal. and the terminal device is provided with means for synchronizing the received frame synchronization signal, further comprising a signal generation circuit for generating the same signal as the frame synchronization signal in the conversion section of the concealment device, A phase adjustment circuit that adjusts the time difference between the output signal and the frame synchronization signal, and a synchronization circuit that synchronizes the two signals in the demodulation section are attached, and each of the frame synchronization signals is used to perform secrecy synchronization. A secret synchronization monitoring method characterized by the ability to monitor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59047360A JPS60190045A (en) | 1984-03-12 | 1984-03-12 | Supervisory system of ciphering synchronization |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59047360A JPS60190045A (en) | 1984-03-12 | 1984-03-12 | Supervisory system of ciphering synchronization |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60190045A true JPS60190045A (en) | 1985-09-27 |
| JPH0446495B2 JPH0446495B2 (en) | 1992-07-30 |
Family
ID=12772952
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59047360A Granted JPS60190045A (en) | 1984-03-12 | 1984-03-12 | Supervisory system of ciphering synchronization |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60190045A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63290427A (en) * | 1987-05-22 | 1988-11-28 | Matsushita Electric Ind Co Ltd | Cryptographic device |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000286833A (en) * | 1999-03-31 | 2000-10-13 | Mitsubishi Electric Corp | Communication system and communication method |
-
1984
- 1984-03-12 JP JP59047360A patent/JPS60190045A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63290427A (en) * | 1987-05-22 | 1988-11-28 | Matsushita Electric Ind Co Ltd | Cryptographic device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0446495B2 (en) | 1992-07-30 |
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