JPH063896B2 - Digital code conversion circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to a digital signal code conversion circuit in a terminal relay station in which a terminal device having a digital code conversion circuit is continuously installed, and in particular, each stage section. The present invention relates to a digital code conversion circuit of the receiving end system when the same scramble pattern is adopted.

[Prior art and its problems]

The code conversion circuit for digital signals in the terminal relay station has two code conversion circuits, a transmission end system and a reception end system, and one transmission line section is formed with a transmission line in between. The connection with the next section is made directly or via a short connecting line. The present invention relates to the code conversion circuit of the receiving end system, but in describing the code conversion device according to the prior art, the transmission end system will also be described in order to clarify the technical contents. .

FIG. 2 is a block diagram of one stage section of a conventional digital code conversion circuit, in which (A) shows a sending end system and (B) shows a receiving end system. In the transmission end system (A), the signal a received from the carrier terminal device or the preceding transmission path section is converted by the stuffing circuit 11 and the transmission end system timing generation circuit 12 into a digital synchronization conversion signal together with a timing signal b required for synchronization. Signal c synchronized to the transmission line frequency
Is scrambled by the scramble circuit 13 with the scramble pattern d generated from the timing generating circuit 12, and the scrambled signal e is transmitted as a signal f to a transmission line (not shown) via the modulator / transmitter 14. This scrambling is performed to facilitate the timing extraction in the receiving system (B) and to smooth the spectrum after modulation.

Next, in the receiving system (B), the signal f received from the transmission line is
Is inputted to the frame synchronization circuit 16 via the receiver / demodulator 15 to become a demodulated signal g equal to the signal e on the sending end side. In the frame synchronization circuit 16, frame synchronization is established in order to know the scramble pattern signal position in the sending end system and the synchronization conversion signal position necessary for stuffing. The frame synchronization signal h for which this frame synchronization is established
The receiving end system timing generation circuit 17 is controlled by the timing signal i synchronized with the sending end system timing generation circuit 12.
And a descramble pattern j is generated. At the same time, the demodulated signal g is descrambled with the descramble pattern j by the descramble circuit 18 to be restored to the same signal k as the stuffing circuit output signal c of the sending end system, and input to the destuffing circuit 19. The destuffing circuit 19 performs the reverse operation of the stuffing circuit 11 of the sending end system by the timing signal i from the timing generating circuit 23 of the receiving end system to restore the input signal a, and the sending end portion ((A) of the next stage section. Output signal l directly or via a connecting line
Is sent as. The connecting line is short on the same desk or in the same room.

In the above signal transmission, when a transmission path failure, particularly a failure such that the demodulated signal g becomes a constant logical value "1" or "0" or a signal string with a markedly deviated mark rate, for example, A failure occurred in the transmission line including the component devices such as the output failure due to the circuit failure in the demodulator, the demodulator input carrier signal failure due to the receiver failure, and the unmodulated wave signal transmission status due to the modulator or transmitter failure. In this case, the frame synchronization circuit 16 does not establish frame synchronization, and the receiving end system timing generation circuit 17 cannot be controlled. At this time, the receiving-end system timing generation circuit 17 operates as an original timing generation circuit which is not in synchronization with the sending-end system timing generation circuit 12, and therefore the descramble circuit output signal k that descrambles the demodulated signal g is It remarkably resembles the sending end scramble pattern d. If the demodulated signal g has a constant logical value "0" or "1", the signal is the same as or inverted from the scrambling pattern of the sending end system.

When the signal as described above is sent to the next stage transmission line section as the output signal 1 through the destuffing circuit 19, the same scramble pattern is adopted in each stage section, so that the next stage transmission line section Due to the scrambling function in the sending end system, the scramble circuit output signal (corresponding to the output signal e in FIG. 2 (A)) becomes a constant logical value or a signal sequence with a marked mark ratio. That is, the scramble function is lost. Therefore, when modulation is performed using such a signal sequence, it becomes impossible to extract the timing at the receiving end system in the next stage transmission line section, which causes a transmission line failure, and the signal spectrum in the next stage transmission line section. Will be significantly distorted. That is, not only is the transmitted data meaningless, but a failure of the transmission path is induced, and timing extraction cannot be performed reliably.

The above problem does not occur if the system configuration has different scramble patterns depending on the section, but almost the same scramble pattern is used in the actually used configuration.

[Object of the Invention]

Therefore, an object of the present invention is to induce a transmission line failure in the next stage section by a transmission line failure in the preceding stage section of a subordinately connected digital transmission line in a digital code conversion circuit adopting the same scramble pattern in each stage section. It is to provide a digital code conversion circuit that can prohibit this.

[Structure of Invention]

In order to achieve the above-mentioned object, the circuit of the present invention affects the output signal of the receiving end system digital code conversion circuit to the transmitting end system digital code conversion circuit of the next stage section in the case where a transmission path failure in the preceding section occurs. It is designed to be converted into a non-specific signal.

That is, according to the present invention, if the reference numerals of FIG. 1 are added for reference, a means (21) for receiving and demodulating a signal scrambled by a scramble pattern common to each stage section in the transmission end system, and demodulated. A frame synchronization circuit (22) for performing frame synchronization of the received signal, means (23) for issuing a receiving end system timing signal and a descramble pattern every time frame synchronization is achieved, and the demodulated signal for the descramble pattern and the descramble. Means (2
4) and a means (25) for outputting a signal obtained by destuffing the descrambled signal with the timing signal, when the frame synchronization circuit loses frame synchronization in the digital code conversion circuit of the receiving end system. And a function (26) for issuing a specific signal having a pattern different from the descramble pattern, and selecting the destuffed signal when the frame synchronization circuit is in frame synchronization, and when the frame synchronization is lost. A switching function for selecting the specific signal and outputting it as a circuit output (27)
It is possible to obtain a digital code conversion circuit characterized by adding and.

〔Example〕

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. Receiver / demodulator 21, frame synchronization circuit 22, receiving end system timing generation circuit 23, descrambling circuit 24,
The portion including the destuffing circuit 25 is the same as that of the conventional apparatus shown in FIG. 2, and therefore the basic operation thereof is also the same as that of the conventional apparatus shown in FIG. However, the present invention is different from the conventional one in that when the frame synchronization circuit 22 does not establish frame synchronization, that is, when a transmission path failure occurs, the frame synchronization circuit 22 outputs a frame synchronization loss signal m to specify To generate a specific signal n by controlling the specific signal generating circuit 26 for generating a specific signal. At this time, it goes without saying that the specific signal n needs to be a signal of a pattern other than the scramble / descramble pattern of the transmission end system or reception end system timing generation circuits 12 and 23. For example, it may be 101010 ... Or 1111 ... Furthermore, for example, when using a 9-stage PN pattern signal for a circuit, you may use a PN pattern signal of another stage. On the other hand, by controlling the frame desynchronization signal m, the switching circuit 27 switches from the destuffing circuit output signal 1 to the specific signal n and sends it as the output signal 0 to the next stage transmission line section. This signal 0 becomes a signal sequence randomized by the scrambling function in the sending end system scramble circuit (corresponding to FIG. 13) in the next stage transmission line section, and the modulation operation is performed by this signal sequence.

As described above, when a transmission line failure occurs, the signal sent to the next stage transmission line section is sent to the next stage by converting it to a specific signal instead of the output signal of the receiving end system digital code conversion circuit. Although the signal does not make sense as data, a digital code conversion circuit configuration that retains the scrambling effect in the next-stage transmission path section and does not transmit the preceding-stage section transmission path failure to the next-stage transmission path section becomes possible.

Although the specific signal generating circuit 26 and the switching circuit 27 are used in the above description, the normal destuffing circuit 2 is usually used.
Since the buffer memory circuit 5 is provided, by controlling the output of the buffer memory with the frame-sync-out signal m, it is possible to easily have a function of generating the specific signal n and a switching circuit operation function. . Further, the problem described above does not occur if the adjacent sections adopt different scramble / descramble patterns, but as described above, such a system does not actually exist. Not generally used.

〔The invention's effect〕

As described above, according to the present invention, even if a transmission path failure occurs in the preceding section of a digital transmission path that is cascade-connected, it is possible to prevent the transmission path failure in the next section from being induced.

[Brief description of drawings]

FIG. 1 is a block diagram of a digital code conversion circuit of a receiving end system which is an embodiment of the present invention, and FIG. 2 is a block diagram of an example of a conventional digital code conversion circuit. Symbol: 11 is a stuffing circuit, 12 is a transmission end system timing generation circuit, 13 is a scramble circuit, 14 is a modulator / transmitter, 21 is a receiver / demodulator, 22 is a frame synchronization circuit, and 23 is a reception end system timing generator. A circuit, 24 is a descrambling circuit, 25 is a destuffing circuit, 26 is a specific signal generating circuit, and 27 is a switching circuit.

Claims (1)

[Claims] 1. A means for receiving and demodulating a signal scrambled by a scrambling pattern common to each stage section in a transmission end system, a frame synchronization circuit for frame-synchronizing the demodulated signal, and each time frame synchronization is established. Means for issuing a receiving end system timing signal and a descramble pattern; means for descrambling the demodulated signal with the descramble pattern; and means for outputting a destuffed signal of the descrambled signal from the timing signal. In a receiver end type digital code conversion circuit having a circuit for generating a specific signal of a pattern different from the descrambling pattern when the frame synchronization circuit loses frame synchronization, and the frame synchronization circuit for frame synchronization Select the destuffed signal A digital code conversion circuit further comprising a switching circuit for selecting the specific signal and outputting it as a circuit output when the frame synchronization is lost.