JPS60190015A - Integrated circuit - Google Patents

Integrated circuit

Info

Publication number
JPS60190015A
JPS60190015A JP59045437A JP4543784A JPS60190015A JP S60190015 A JPS60190015 A JP S60190015A JP 59045437 A JP59045437 A JP 59045437A JP 4543784 A JP4543784 A JP 4543784A JP S60190015 A JPS60190015 A JP S60190015A
Authority
JP
Japan
Prior art keywords
circuit
output
signal
bpf
time constant
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59045437A
Other languages
Japanese (ja)
Other versions
JPH0325052B2 (en
Inventor
Mitsuru Kudo
満 工藤
Kuniaki Miura
三浦 邦昭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP59045437A priority Critical patent/JPS60190015A/en
Publication of JPS60190015A publication Critical patent/JPS60190015A/en
Publication of JPH0325052B2 publication Critical patent/JPH0325052B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00Networks using active elements
    • H03H11/02Multiple-port networks
    • H03H11/04Frequency selective two-port networks
    • H03H11/12Frequency selective two-port networks using amplifiers with feedback
    • H03H11/1217Frequency selective two-port networks using amplifiers with feedback using a plurality of operational amplifiers

Landscapes

  • Networks Using Active Elements (AREA)

Abstract

PURPOSE:To obtain an integrated active BPF circuit having a desired characteristic by providing a limiter circuit to an output section of the active BPF composing a resistor, a capacitor and an amplifier so as to absorb the fluctuation of an output amplitude depending on variation in a time constant circuit. CONSTITUTION:The variation of the output amplitude of the BPF circuit attended with the changeover is suppressed by connecting the limiter circuit 16 to an output terminal of the active BPF with time constant switching circuits 12, 13. An input signal from an input terminal 21 is inputted to a base of Trs Q1, Q2 constituting a differential amplifier in the circuit 16 and only the DC component of input signal is propagated because of the capacitance 19. The difference of the input signal is multiplied by a factor of the gain at the differential amplifier and the signal is outputted from a terminal 15 while the upper and lower limit of the output signal is limited because this circuit has a high gain. Thus, even if the input signal amplitude is fluctuated, a limit is given over the output signal by increasing sufficiently the gain of the differential amplifier.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は、IC上の集積化回路に係り、特に帯域通過フ
ィルタ(以下 BPFと略す)に好適な集積化フィルタ
に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an integrated circuit on an IC, and particularly to an integrated filter suitable for a band pass filter (hereinafter abbreviated as BPF).

〔発明の背景〕[Background of the invention]

電気回路の集積化(モノリシックIC化、以下単にIC
化と略す)が進むにつれ、外付のブロックフィルタのI
C化が回路基板の小形化。
Integration of electrical circuits (monolithic IC, hereinafter simply IC)
(abbreviated as "I") progresses, the I
C conversion leads to the miniaturization of circuit boards.

低コスト化を実現する上で重要な課題となりつつある。This is becoming an important issue in achieving cost reduction.

従来のフィルタは大部分がインダクタンスL、容量C1
抵抗Rで構成されているが、インダクタンスしはIC化
が娯しいため従来形式のフィルタの集積化は田畑である
。このため容量C1抵抗托と増幅器で構成6]能なアク
ティブフィルタがIC化には通している。第1図に帰還
形アクティブB P Fのブロック図の一例を示し以下
説明する。1は信号入力端、4は伯゛号出力端、2は利
得に、の帰還増幅器、6は利得に2の帰還増幅器、抵抗
へ〜塊と容量C1〜C4は時定数用である。抵抗1へと
14.容量CIとC3と帰還増幅器2とで2次形の高域
通過フィルタ(以下l」PFと略す)を、抵抗1(うと
Iζ、容量C8とC2と帰還増幅器6とで2次形の低域
通過フィルタ(以下L P Fと略す)をそれぞれ構成
し、前記HPFとL P F”を組み合せることにより
BPFを構成する。
Most conventional filters have an inductance L and a capacitance C1.
Although it is composed of a resistor R, it is difficult to integrate an inductance into an IC, so it is difficult to integrate a conventional filter. For this reason, an active filter consisting of a capacitor C1 resistor and an amplifier has been implemented as an IC. An example of a block diagram of a feedback type active BPF is shown in FIG. 1 and will be described below. 1 is a signal input terminal, 4 is a signal output terminal, 2 is a gain and a feedback amplifier, 6 is a gain and a feedback amplifier of 2, a resistor and capacitors C1 to C4 are for time constants. Resistance 1 to 14. Capacitors CI and C3 and feedback amplifier 2 form a quadratic high-pass filter (hereinafter abbreviated as PF), and resistor 1 (Iζ), capacitors C8 and C2, and feedback amplifier 6 form a quadratic low-pass filter. Pass filters (hereinafter abbreviated as L P F) are respectively configured, and a BPF is configured by combining the HPF and L P F''.

しかし上記構成のBPFをIC化する場合、バラつきの
問題が生じる。すなわちIC内の容量値、抵抗値は半導
体内の不純物濃度、マスクずれなどによるバラつきの影
響を受け、−例として Cの絶対値 ±20チ 凡の絶対値 115% などの大きな変動を有する。したがって第1図のBPF
のピーク周波数fpも第2図のようにaからbの範囲で
変動し、上記例では最悪時fpは±35チ変動すること
になり実用化は極めて困難である。この素子値バラつき
の対策としては、ICチップ上でレーザトリミングなど
により抵抗値を変化させ、バラつきを吸収することも実
施されているが、精度、歩留り、コストの面などでまだ
多くの問題点があり、一般民生用ICにはほとんど実用
化されていない。
However, when converting the BPF with the above configuration into an IC, a problem of variation occurs. That is, the capacitance value and resistance value within the IC are affected by variations due to impurity concentration within the semiconductor, mask misalignment, etc., and have large fluctuations, such as an absolute value of C of about ±20% and an absolute value of 115%. Therefore, the BPF in Figure 1
The peak frequency fp also varies in the range from a to b as shown in FIG. 2, and in the above example, the worst case frequency fp varies by ±35 degrees, making it extremely difficult to put it into practical use. As a countermeasure to this variation in element values, attempts have been made to change the resistance value on the IC chip by laser trimming, etc. to absorb the variation, but there are still many problems in terms of accuracy, yield, cost, etc. However, it has hardly been put into practical use in general consumer ICs.

またアクティブフィルタを構成する容量に接合容量を用
い、接合容量のもつ容量絶対値のバイアス依存性を利用
し容量値を可変して、抵抗値及び容量値の絶対値バラつ
きを吸収する方法もある。その−例であるアクティブ4
次BPFの回路例を第6図に示し、以下説明する。5は
入力信号源、6は可変電圧源、7は利得に3の差動増幅
器、8は利得に4(K4−1)の増幅器、9は利得Ks
の差動増幅器、10は出力信号端、11は定電圧源、抵
抗に〜風と容量C1,C,は第1図と同じくフィルタの
時定数回路を構成するものである。鳥〜賜は抵抗で、抵
抗1−〜賜は増幅器7〜90入力端に直流電位を与える
ものである。
Another method is to use a junction capacitor as the capacitor constituting the active filter, and to vary the capacitance value by utilizing the bias dependence of the absolute capacitance value of the junction capacitor, thereby absorbing variations in the absolute values of the resistance value and the capacitance value. Active 4 is an example of this.
An example of the BPF circuit is shown in FIG. 6 and will be described below. 5 is an input signal source, 6 is a variable voltage source, 7 is a differential amplifier with a gain of 3, 8 is an amplifier with a gain of 4 (K4-1), 9 is a gain Ks
, a differential amplifier 10, an output signal terminal 11, a constant voltage source 11, a resistor, a capacitance C1, and a capacitance C1 constitute the time constant circuit of the filter as in FIG. The resistors 1 to 1 are resistors, and the resistors 1 to 1 apply a DC potential to the input terminals of the amplifiers 7 to 90.

容量C6は結合容量である。なお容量C,、C,は接合
容量で構成されている。上記の構成において、増幅器の
入力インピーダンスを無限大、出力インピーダンスを零
とする理想増幅器とすると差動増幅器702入力端の端
子電圧は常に等しくなり、差動増幅器7の出力端電圧は
一定となる。
Capacitance C6 is a coupling capacitance. Note that the capacitances C, , C, are composed of junction capacitances. In the above configuration, if the amplifier is an ideal amplifier with infinite input impedance and zero output impedance, the terminal voltages at the input terminal of the differential amplifier 702 are always equal, and the output terminal voltage of the differential amplifier 7 is constant.

し、たがって可変電圧源6の電位変動により容量C3と
C!の両極にかかるバイアス電位が等しく変化し、容量
C2とC1の容量絶対値がバイアス電位に応じて変化し
て、時定数回路のバラつきが吸収できる。さらに増幅器
8を入力端電位と出力端電位が等しくなるバッファー回
路とすると、差動増幅器902つの入方端直流電位も等
しくなり、差動増幅器9の出力端電位は一定となる。
Therefore, due to the potential fluctuation of the variable voltage source 6, the capacitors C3 and C! The bias potential applied to both poles changes equally, and the absolute capacitance values of capacitors C2 and C1 change in accordance with the bias potential, so that variations in the time constant circuit can be absorbed. Further, if the amplifier 8 is a buffer circuit in which the input terminal potential and the output terminal potential are equal, the input terminal DC potentials of the two differential amplifiers 90 will also be equal, and the output terminal potential of the differential amplifier 9 will be constant.

また定電圧源11の出力電位を差動増幅器9の出力端電
位と等しくなるように構成すると、可変電圧源6の出力
電位の変化に応じて容量Csと04の印加電圧が等しく
変化し、それに伴い容量の絶対値も変化する。したがっ
てLPF部を構成する時定数回路のバラつきも町変電圧
源乙の調整により吸収できる。
Furthermore, if the output potential of the constant voltage source 11 is configured to be equal to the output terminal potential of the differential amplifier 9, the applied voltages of the capacitors Cs and 04 will change equally according to changes in the output potential of the variable voltage source 6, and The absolute value of capacitance also changes accordingly. Therefore, variations in the time constant circuit constituting the LPF section can be absorbed by adjusting the variable voltage source B.

ところが接合容量のバイアス電圧による容量値依存性は
第4図に示す一例のような特性である。この図かられか
るように、バイアス電圧変化による接合容量絶対値変化
の感度は低く、第4図では容量値を±35チ変化させる
にはバイアス電圧を約4V程度変化させな(てはいけな
い。
However, the dependence of the junction capacitance on the bias voltage on the capacitance value has a characteristic as shown in an example shown in FIG. As can be seen from this figure, the sensitivity of changes in the absolute value of junction capacitance due to changes in bias voltage is low, and in FIG. 4, in order to change the capacitance value by ±35 degrees, the bias voltage must not be changed by about 4V.

このため、たとえば電源電圧が5■の場合、回路動作マ
ージンの制約から可変電圧源6の電位を4■も可変する
事は不可能となり、時定数回路のバラつき±65チを吸
収することは不可能となる。
For this reason, for example, when the power supply voltage is 5 µ, it is impossible to vary the potential of the variable voltage source 6 by 4 µ due to circuit operation margin constraints, and it is impossible to absorb the variation of ±65 µ in the time constant circuit. It becomes possible.

そこで第5図に示す時定数切替回路の一例を第3図のB
PF部とLPF部の時定数回路に設けて、時定数回路の
バラつきを吸収している。
Therefore, an example of the time constant switching circuit shown in FIG.
It is provided in the time constant circuits of the PF section and LPF section to absorb variations in the time constant circuits.

第5図を説明する。第5図のa)が)l P F部。FIG. 5 will be explained. a) in Fig. 5 is)l P F section.

b)がLPF部の時定数回路である。12.13は時定
数切替スイッチ、14は切替信号人カ端、容量Ca、C
bは第6図で容ftC1に相当するものである。抵抗几
a、Rbは第3図で抵抗へに相当するものである。第6
図におけるH P fi’部とLPF部の共振周波数f
on、 foLと回路の良さQHlQLは fOH−□・・・(1) 24ハW人τ言7 と表わされるので、共振周波数fOH、fOLの容量C
1と抵抗へに相当する容量CaとCb 、抵抗比aと肋
の絶対値を各々約+40係と約−25俤のところに設定
することにより共振周波数foe、 fOLはともにセ
ンター値に比べ約+15係はどズレる。この後、接合容
量の調整により共振周波数fOH1fOLを±20係移
動することにより、時定数回路のバラつぎ±65チを吸
収することができる。
b) is the time constant circuit of the LPF section. 12.13 is a time constant changeover switch, 14 is a changeover signal terminal, capacitance Ca, C
b corresponds to the capacity ftC1 in FIG. Resistors a and Rb correspond to the resistors in FIG. 6th
The resonance frequency f of the H P fi' part and the LPF part in the figure
on, foL and the quality of the circuit QHlQL are expressed as fOH-□...(1) 24haWpersonτ7, so the capacitance C of the resonance frequency fOH, fOL
By setting the capacitances Ca and Cb corresponding to 1 and the resistance, the resistance ratio a, and the absolute value of the rib to about +40 and about -25 degrees, respectively, the resonant frequencies foe and fOL are both about +15 compared to the center value. The person in charge is out of sync. Thereafter, by adjusting the junction capacitance and moving the resonant frequency fOH1fOL by a factor of ±20, it is possible to absorb the variation of ±65 in the time constant circuit.

ただし第5図に示すような時定数切替回路を設けると削
成(21、(2’)かられかるように容量C1とC7の
比と、抵抗為と塊の比が変わり、容量Caと抵抗Ra側
と、容量Cbと抵抗Rb側で回路の良さを示すQの値が
異なることになる。このため、第5図のような時定数切
替回路を設けた第3図のようなアクティブBPF回路で
は、Qの値の変動により出力信号振幅がバラつくという
問題を生じる。
However, if a time constant switching circuit as shown in Fig. 5 is provided, the ratio of capacitances C1 and C7 and the ratio of resistance to mass will change, as shown in (21, (2')), and the ratio of capacitance Ca to resistance will change. The value of Q, which indicates the quality of the circuit, will be different between the Ra side and the capacitor Cb and resistor Rb side.For this reason, an active BPF circuit as shown in Fig. 3 with a time constant switching circuit as shown in Fig. 5 is used. However, a problem arises in that the output signal amplitude varies due to variations in the Q value.

上記回路をたとえば家庭用VTRにおけるVHS (V
ideo Home System )方式の色信号処
理系における通過中心周波数が4.21■1zのB P
 F(以下4.21MHzBPFと略す)に適用する。
For example, if the above circuit is used in a home VTR, VHS (V
B P with a passing center frequency of 4.21■1z in the color signal processing system of the ideo Home System) method.
F (hereinafter abbreviated as 4.21MHz BPF).

この時このB P F出力を入力とする掛算器では4.
21M)Jzの信号で色信号をスイッチングするので、
4、211(zの信号振幅がバラつ(と、振幅レベルが
小さい時には変換効率の低下を招き、振幅レベルが大き
い時は4.21 MHz 4’t4号のもれとなって色
信号の妨害となるという問題を生じる。これらの障害は
、再生画面上での色信号のS/Nの低下とか、ビート妨
害となり著しくVTRの再生画面を見苦しいものとして
いた。
At this time, in the multiplier that receives this BPF output as input, 4.
21M) Since the color signal is switched using the Jz signal,
4, 211 (z signal amplitude varies (and when the amplitude level is small, the conversion efficiency will decrease, and when the amplitude level is large, the 4.21 MHz 4't4 will leak and interfere with the color signal) These problems cause a drop in the S/N ratio of the color signal on the playback screen and a beat disturbance, making the playback screen of the VTR extremely unsightly.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、上記した欠点をなくすアクティブフィ
ルタ集積回路を提供することにある。
The object of the invention is to provide an active filter integrated circuit which eliminates the above-mentioned drawbacks.

〔発明の概要〕[Summary of the invention]

本発明は時定数切替回路を内蔵したアクティブBPII
′回路における出力信号の伽輻レベルの変動をな(す回
路構成とする。
The present invention is an active BPII with a built-in time constant switching circuit.
'The circuit configuration is such that the output signal level in the circuit fluctuates.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の一実施例であるブロック図を第6図によ
り説明する。第6図において第5図と第5図と同符号、
同番号は同じ構成部品を示す。16はリミッタ回路、1
5は出力端である。
Hereinafter, a block diagram of an embodiment of the present invention will be explained with reference to FIG. In FIG. 6, the same reference numerals as in FIG. 5 and FIG.
Like numbers indicate like components. 16 is a limiter circuit, 1
5 is an output end.

本実施例のように時定数切替回路付アクティブB P 
Fの出力端にリミッタ回路16を結合することにより、
切替え動作に伴うBPFl路の出力振幅のバラつきが抑
えることができる。
As in this example, an active B P with a time constant switching circuit is used.
By coupling the limiter circuit 16 to the output terminal of F,
Variations in the output amplitude of the BPF1 path due to the switching operation can be suppressed.

VTRの色信号処理回路の4.21 Mk−Jz B 
P Fに本実施例のアクティブBPF回路を用いること
により、再主画面でのS/Nの低下やビート妨害を受け
ない良好な画面が得られる。
4.21 Mk-Jz B of color signal processing circuit of VTR
By using the active BPF circuit of this embodiment in the PF, a good screen can be obtained that is free from S/N reduction and beat disturbance on the main screen.

第7図に本発明に用いられるリミッタ回路の一実施例を
示す。15は出力端、16はリミッタ回路、17と18
は定電流源、19は平滑用コンデンサ、20は定電圧W
121は信号入力端、几8〜10は抵抗、Q1〜Q3は
トランジスタである。第7図の回路の動作を説明する。
FIG. 7 shows an embodiment of a limiter circuit used in the present invention. 15 is the output terminal, 16 is the limiter circuit, 17 and 18
is a constant current source, 19 is a smoothing capacitor, and 20 is a constant voltage W.
121 is a signal input terminal, 8-10 are resistors, and Q1-Q3 are transistors. The operation of the circuit shown in FIG. 7 will be explained.

信号入力端21かもの入力信号は、差動増幅器を構成す
るトランジスタQ1とQ2のベースに抵抗比8とR9を
介して入力される。ただしトランジスタQ2のペース端
には容量には容t19が接続されているので、入力信号
は平滑され直流成分のまが伝搬する。差動増#jJ器で
は入力信号差が利得倍されるが、本回路は高利得なため
出力信号が上下限で制限された波形となり、トランジス
タQ3のエミツタポロワアーから出力される。したかっ
て入力端21からの入力信号振幅がバラついても、差動
増幅器の利得を充分大きくしておくことにより、出力端
15かもの出力信号はリミフタのかかった一定娠幅の信
号となる。
An input signal from the signal input terminal 21 is inputted to the bases of transistors Q1 and Q2 constituting a differential amplifier via resistance ratios 8 and R9. However, since the capacitor t19 is connected to the lead end of the transistor Q2, the input signal is smoothed and the DC component is propagated. In the differential amplifier #jJ, the input signal difference is multiplied by the gain, but since this circuit has a high gain, the output signal has a waveform limited by the upper and lower limits, and is output from the emitter lower of the transistor Q3. Therefore, even if the amplitude of the input signal from the input terminal 21 varies, by making the gain of the differential amplifier sufficiently large, the output signal from the output terminal 15 becomes a signal with a constant amplitude applied by the limiter.

また第6図では、時定数切替回路を内蔵したアクティブ
BPF回路を示し増幅器を入力インピーダンス無限大、
出力インピーダンス零の理想増幅器と仮定し話を進めた
が、実際の回路では入力インピーダンスは無限大とはな
らず、また出力インピーダンスは零ではない。さらに集
積化回路に特有な寄生素子によるIC内素子の特性劣化
やバラつきが生じる。このため時定数切替回路のない第
8図に示すようなアクティブBPF回路においてもBP
F部での出力信号振幅がバラつぎ、リミッタ回路16を
加えることで出力信号振幅のバラつきを生じなくするこ
とができる。
Fig. 6 shows an active BPF circuit with a built-in time constant switching circuit, and an amplifier with infinite input impedance.
Although we have proceeded with the discussion assuming an ideal amplifier with zero output impedance, in actual circuits, the input impedance is not infinite, and the output impedance is not zero. Further, characteristics of elements within the IC deteriorate and vary due to parasitic elements specific to integrated circuits. Therefore, even in an active BPF circuit as shown in Fig. 8 without a time constant switching circuit, the BP
Since the output signal amplitude at the F section varies, by adding the limiter circuit 16, it is possible to eliminate the variation in the output signal amplitude.

なおりPF部の出力にリミッタ回路を付加することによ
り、リミッタ回路出力信号の周波数成分として新もだに
基本波の奇数次の高調波成分が出るがVTRでは帯域外
となり問題とならない。
By adding a limiter circuit to the output of the PF section, odd-numbered harmonic components of the fundamental wave are generated as frequency components of the limiter circuit output signal, but they are out of the band of the VTR and do not pose a problem.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明によれば、抵抗と容量と増
幅器からなるアクティブBPFの時定数回路のバラつぎ
Kよる出力信号振幅のバラつきを、BPF出力部にリミ
ッタ回路を設けることで吸収でき、所望のBPF%性を
持つ集積化アクティブBPF回路が得られ、従来外付部
品であったブロックフィルタを集積化することができる
As explained above, according to the present invention, variations in output signal amplitude due to variations in the time constant circuit of an active BPF consisting of a resistor, a capacitor, and an amplifier can be absorbed by providing a limiter circuit in the BPF output section. An integrated active BPF circuit having a desired BPF percentage can be obtained, and a block filter, which has conventionally been an external component, can be integrated.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はアクティブBPFの一例を示す回路図、第2図
は第1図のフィルタの特性図、第3図は接合容量を用い
たアクティブBPF’回路の一例を示す回路図、第4図
は接合容量の特付図、第5図は時定数切替回路の一例を
示す回路図、第6図は本発明を採用したアクティブB 
P l”回路の一実施例を示す回路図、第7図はリミッ
タ回路の一例を示す回路図、第8図は本発明を利用した
アクティブBPF回路の他の実施例を示す回路図である
。 塊、為lR51風、Ra、几b・・・時屋数を構成1−
る抵抗、 C,、C,、C,、C,、Ca、Cb −・・時定数を
構成する容量、 6・・・q変電圧源、 12、13−06時定数切替回路、 16・・・リミッタ回路。 鵠人弁理士高橋明夫 % 1 l 第 ?閃 第 3 l 第50 第 4 口
Fig. 1 is a circuit diagram showing an example of an active BPF, Fig. 2 is a characteristic diagram of the filter shown in Fig. 1, Fig. 3 is a circuit diagram showing an example of an active BPF' circuit using junction capacitance, and Fig. 4 is a circuit diagram showing an example of an active BPF' circuit using junction capacitance. A special diagram of junction capacitance, Figure 5 is a circuit diagram showing an example of a time constant switching circuit, and Figure 6 is an active B adopting the present invention.
FIG. 7 is a circuit diagram showing an example of a limiter circuit, and FIG. 8 is a circuit diagram showing another example of an active BPF circuit using the present invention. Mass, Tame IR51 wind, Ra, 几b... Tokiya number is composed of 1-
Resistance, C,, C,, C,, C,, Ca, Cb - Capacitance constituting time constant, 6...q variable voltage source, 12, 13-06 Time constant switching circuit, 16...・Limiter circuit. Kueto Patent Attorney Akio Takahashi% 1 l No. ? Sen No. 3 l No. 50 No. 4

Claims (1)

【特許請求の範囲】 1、 半導体ウェハ上に構成される抵抗と容量と増幅器
からなるアクティブ帯域通過フィルタにおいて、前記帯
域通過フィルタの出力段にリミッタ回路を設けたことを
特徴とする集積回路。 2、 色信号を低域周波数に周波数変換して記録再生す
る磁気記録再生装置において、周波数変換用搬送波を発
生する掛算器の出力信号を入力信号とする上記特許請求
の範囲第1項記載の集積回路。
[Scope of Claims] 1. An integrated circuit comprising an active bandpass filter constructed on a semiconductor wafer and comprising a resistor, a capacitor, and an amplifier, characterized in that a limiter circuit is provided at the output stage of the bandpass filter. 2. In a magnetic recording and reproducing device that records and reproduces a color signal by frequency converting it to a low frequency, the integrated device according to claim 1, wherein the output signal of a multiplier that generates a carrier wave for frequency conversion is used as an input signal. circuit.
JP59045437A 1984-03-12 1984-03-12 Integrated circuit Granted JPS60190015A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59045437A JPS60190015A (en) 1984-03-12 1984-03-12 Integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59045437A JPS60190015A (en) 1984-03-12 1984-03-12 Integrated circuit

Publications (2)

Publication Number Publication Date
JPS60190015A true JPS60190015A (en) 1985-09-27
JPH0325052B2 JPH0325052B2 (en) 1991-04-04

Family

ID=12719290

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59045437A Granted JPS60190015A (en) 1984-03-12 1984-03-12 Integrated circuit

Country Status (1)

Country Link
JP (1) JPS60190015A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5646386A (en) * 1979-09-25 1981-04-27 Toshiba Corp Dropout compensating circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5646386A (en) * 1979-09-25 1981-04-27 Toshiba Corp Dropout compensating circuit

Also Published As

Publication number Publication date
JPH0325052B2 (en) 1991-04-04

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