JPS60189967A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS60189967A JPS60189967A JP59045666A JP4566684A JPS60189967A JP S60189967 A JPS60189967 A JP S60189967A JP 59045666 A JP59045666 A JP 59045666A JP 4566684 A JP4566684 A JP 4566684A JP S60189967 A JPS60189967 A JP S60189967A
- Authority
- JP
- Japan
- Prior art keywords
- region
- transistor
- channel
- parasitic
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 230000003071 parasitic effect Effects 0.000 claims abstract description 21
- 230000006798 recombination Effects 0.000 claims abstract description 10
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 239000013078 crystal Substances 0.000 claims description 5
- 230000000694 effects Effects 0.000 abstract description 21
- 239000000758 substrate Substances 0.000 abstract description 16
- 238000005215 recombination Methods 0.000 abstract description 9
- 238000009413 insulation Methods 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract description 4
- 238000002955 isolation Methods 0.000 abstract description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract 1
- 108091006146 Channels Proteins 0.000 description 34
- 230000020169 heat generation Effects 0.000 description 6
- 239000000969 carrier Substances 0.000 description 5
- 230000015556 catabolic process Effects 0.000 description 5
- 239000012212 insulator Substances 0.000 description 5
- 239000012535 impurity Substances 0.000 description 4
- -1 Oxygen ions Chemical class 0.000 description 3
- 230000000295 complement effect Effects 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 230000006378 damage Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000001066 destructive effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7824—Lateral DMOS transistors, i.e. LDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys
- H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/30—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface
- H01L29/32—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface the imperfections being within the semiconductor body
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は高耐圧特性を有するＭＯｓトランジスタに関す
る。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a MOS transistor having high breakdown voltage characteristics.
（従来技術）
高耐圧特性を有するＭＯ日トランジスタの構造としては
、いわゆるＤ８ム（Ｄｉｆｆｕｓｉｏｎ Ｓｅｌｆ−Ａ
ｌｉｇｎ ）構造、■−溝（Ｖ−ｇｒｏｏｖｅ ）構造
、オフセットゲート構造及びこれらの変形構造が知られ
ている。(Prior art) The structure of a MO transistor with high breakdown voltage characteristics is the so-called D8M (Diffusion Self-A
lign) structure, -groove (V-groove) structure, offset gate structure, and modified structures thereof are known.
この内、ＤＳＡ構造は高耐圧素子であシ、かつ集積化が
容易でｓｂチャネル長を短くできるため、高性能（高り
、高ｆＴ）を必要とするＭＯｓトランジスタに幅広く採
用されていた。このＤＳＡ構造のＭＯＳト２ンジスタの
代表的な構造を第１図に示す。以下、この図に従い、従
来構造が有していた欠点を明らかにする吃のである。尚
、以下の説明では半導体に存在する二つの伝導形のうち
、一方を例にとシ進めるが、他方についても同様な結果
を得るものである。支持基板１中に形成されたＵＳＡ
蝉造のＭＯＳ ）ランジスタは、基板の伝導形をＮ形と
した場合、ｖ形の°ドレイン３．Ｐ形のチャネル部４゜
１形のソース５．ゲート部の絶縁膜６．フィールド部の
絶縁膜７．ソース電極８．ゲート電極９゜ドレイン電極
１０．及びコンタクト窓１１などからなっている。動作
状態にシいては、ゲート電極９に印加された入力端子に
よって絶縁膜６の下のチャネル部４にチャネル１２が形
成されて増幅された信号電流が流れると共に、チャネル
部４と基板１で形成されたＰＮ接合の近傍に空乏層１３
が出現し、ソース電極８〜ドしイン電極１０間に印加さ
れた電圧を負担するものである。この時、ソース電極８
及びゲート電極９の一部を絶縁Ｍ７上でチャネル部４よ
り外方に延ばした構造（通常フィールドプレート構造８
１．９１と呼称）とすることは、空乏層１３の絶縁膜７
に近い部分を同様に外方に延ばして電界の集中を防ぐこ
とが可能となり高耐圧化に極めて有利となるものである
。Among these, the DSA structure is a high breakdown voltage element, easy to integrate, and can shorten the sb channel length, so it has been widely used in MOS transistors that require high performance (high, high fT). A typical structure of a MOS transistor having this DSA structure is shown in FIG. Below, we will explain the drawbacks of the conventional structure using this diagram. In the following explanation, one of the two conduction types existing in semiconductors will be taken as an example, but similar results will be obtained with the other type. USA formed in support substrate 1
Semizo's MOS) transistor has a v-type drain when the conduction type of the substrate is N type. P-type channel section 4.1-type source 5. Insulating film at gate part 6. Insulating film in field section7. Source electrode8. Gate electrode 9° Drain electrode 10. and a contact window 11. In the operating state, a channel 12 is formed in the channel portion 4 under the insulating film 6 by the input terminal applied to the gate electrode 9, and an amplified signal current flows through the channel portion 4. A depletion layer 13 is formed near the PN junction.
appears and bears the voltage applied between the source electrode 8 and the in-electrode 10. At this time, the source electrode 8
and a structure in which a part of the gate electrode 9 is extended outward from the channel part 4 on the insulating M7 (normally a field plate structure 8).
1.91) means that the insulating film 7 of the depletion layer 13
This makes it possible to prevent concentration of electric fields by similarly extending the portions close to the outside to the outside, which is extremely advantageous in increasing the withstand voltage.
さて、この構造の素子においては空乏層１３内において
、正孔１４及び電子１５からな゛るキャ０リアの発生が
生ずる。この内篭子１５は基板ｌ中で多数キャリアーと
して振るまうため、あまシ問題と々らないが、正孔１４
はチャネル部４中に流れこみ、チャネル部４の電位を上
ける働き管するものでおる。チャネル部４の電位が変動
するとゲート電極９に印加された大刀信号が変動するこ
ととなシ、正−常な増幅動作が期待できず、素子特性の
劣化をもたらすこととなる。そこで、このようなチャネ
ル電位の変動を防ぐためコンタクト窓１１を用いて、比
較的定電位を有するソース電極８をチャネル部４及びソ
ース５に同時に電気的に接触させる構造とする。Now, in the element having this structure, carriers consisting of holes 14 and electrons 15 are generated within the depletion layer 13. This inner cage 15 acts as a majority carrier in the substrate l, so there is no problem, but the hole 14
flows into the channel portion 4 and serves to increase the potential of the channel portion 4. If the potential of the channel section 4 fluctuates, the long signal applied to the gate electrode 9 will fluctuate, and normal amplification operation cannot be expected, resulting in deterioration of device characteristics. Therefore, in order to prevent such fluctuations in the channel potential, a structure is adopted in which the source electrode 8 having a relatively constant potential is brought into electrical contact with the channel portion 4 and the source 5 at the same time using the contact window 11.
ソース５の下のチャネル部４はいわゆるピンチ抵抗的な
形状となるため、あたかも高抵抗（図中−’ＶＸＩ−記
号で明示）が存在するかのように振るまい、正孔１４の
移動即ち正孔電流が流れた場゛合、ソース５とチャネル
ｓ４のバイアス電圧を与えることとなる。高電圧印加時
に社空乏化された領域が広がるため、キャリアの発生も
多くな）正、孔電流が増大し、ついにはソース５とチャ
ネル部４で形成されたＰＮ接合を順バイアスする程の電
位差が生ずることとなる。さて、このような状態のＤ日
Ａ構造のＭＯＳ トランジスタは本質的なＭＯＢ動作に
加えて、５をエミッタ、４をベース、１及び３をコレク
タとするいわゆる寄生バイボージ動作を伴なうこととな
る。この場合、本来のＭＯＳ ）う゛ンジスタには見ら
れなかった熱暴走による素子の破壊モードが出現する。Since the channel section 4 under the source 5 has a so-called pinch resistance shape, it behaves as if a high resistance (expressed by the symbol -'VXI- in the figure) exists, and the movement of the holes 14, i.e., the positive When a hole current flows, a bias voltage is applied to the source 5 and the channel s4. When a high voltage is applied, the depleted region expands, and more carriers are generated.Positive and hole currents increase, and the potential difference becomes large enough to forward bias the PN junction formed by the source 5 and channel part 4. will occur. Now, in addition to the essential MOB operation, the MOS transistor with the D/A structure in this state is accompanied by a so-called parasitic biborg operation in which 5 is the emitter, 4 is the base, and 1 and 3 are the collectors. . In this case, a destruction mode of the element due to thermal runaway, which was not observed in the original MOS transistor, appears.
即ち、寄生パイボーラド２ンジスタが動作し始め、かつ
チャネル部４に充分な正孔電流が流れ込むと、ソース５
からトランジスタ動作によって、ｈＰ、Ｃ倍の電子がチ
ャネル部４に注入されることとなる。この注入された多
量の電子による電流と空乏層、１３に印加された電圧に
よって発熱が生ずるが、発熱によってｈ７゜示増大する
ため、
「正孔電流の流入−ｈＰＩ倍の電子電流−発熱→ｈｏｌ
ｅの増大→ｈ□倍の電子電流の増大−一層の発熱」
なる正帰還がかかル、ついには発熱に、よる素子の破壊
をひきおこすものである。That is, when the parasitic piborad 2 transistor starts to operate and a sufficient hole current flows into the channel part 4, the source 5
As a result of the transistor operation, hP and C times as many electrons are injected into the channel portion 4. Heat generation occurs due to the current caused by this large amount of injected electrons and the voltage applied to the depletion layer 13, but since the heat generation increases by h7°, "inflow of hole current - electron current times hPI - heat generation → hol
Increasing e→electronic current increasing by h□ times - further heat generation" This is the positive feedback that eventually leads to heat generation and destruction of the element.
（発明の目的）
本発明は前記の如き問題点を解決し、寄生バイポーラ効
果のないＤＳＡ構造のＭＯＳ ）ランジスタを提供する
ことを目的とするものである。(Objective of the Invention) It is an object of the present invention to solve the above-mentioned problems and to provide a MOS transistor having a DSA structure without parasitic bipolar effects.
（発明の構成）
上記の目的を達成するため、本発明はＭＯＥＪ形トラン
ジスタを含む半導体装置において、寄生バイポーラトラ
ンジスタのベース領域に、生成再結合中心を含む領域又
はバンドギャップが周囲の半導体領域に比べて広い領域
が少なくとも形成されたことを特徴とする半導体装置を
発明の要旨とするものである。(Structure of the Invention) In order to achieve the above object, the present invention provides a semiconductor device including an MOEJ transistor, in which a region containing a production recombination center or a band gap is compared to a surrounding semiconductor region in a base region of a parasitic bipolar transistor. The gist of the invention is a semiconductor device characterized in that at least a wide area is formed.
次に本発明の実施例を添附図面について説明する。なお
実施例は一つの例示であって、本発明の精神を逸脱しな
い範囲で、種々の変更あるいは改良を行いうろことは云
うまでもない。Next, embodiments of the present invention will be described with reference to the accompanying drawings. It should be noted that the embodiments are merely illustrative, and it goes without saying that various changes and improvements may be made without departing from the spirit of the present invention.
第２図は本発明の一実施例であシ、複数の素子を同一基
板上に搭載する装置を示したものである。FIG. 2 is an embodiment of the present invention, and shows an apparatus for mounting a plurality of elements on the same substrate.
ここでは、高耐圧化に有利な、いわゆる誘電体分離構造
としているが、通常のこの種の装置と同様、単結晶基板
中に搭載することももちろん可能である。以下の説明で
は相補形の島（Ｐ形とＮ形の島）を有する場合を例とす
る。多結晶８１等からなる支持基板１６中に絶縁膜や牛
絶縁膜等からなる分離膜１７を介して、Ｐ形の島１８及
びＮ形の島１９が設けられている。これらの島の中には
ＰチャネルのＤＳＡ構造ＭＯ８）ランジスタ２０及びＮ
チャネルのＤＳＡ構造のＭＯＳ ）ランジスタ２１が形
成される。２０及び２１はドレイン３．チャネル部４゜
ソース５．ゲート部の絶縁膜６．フィールド部の絶縁膜
７．ソース電極８．ゲート電極９．ドレイン電極１０．
コンタクト窓１１．フィールドプレート８１．９１を有
するほか、いわゆるバックゲート効果を小さくするため
の埋込層２２などからなる。動作状態においては、ゲー
ト電極９の下の絶縁膜６と接する領域にチャネル１２が
形成され、ソース５とドレイン３の間を電気的な導通状
態とし、又ソース５とドレイン３間に印加される電圧を
支える空乏層１３が出現するものである。Here, a so-called dielectric isolation structure is used, which is advantageous for increasing the withstand voltage, but it is of course possible to mount it in a single crystal substrate as in a normal device of this type. In the following description, a case where complementary islands (P-type and N-type islands) are provided will be taken as an example. A P-type island 18 and an N-type island 19 are provided in a support substrate 16 made of polycrystalline 81 or the like with a separation film 17 made of an insulating film, a copper insulating film, etc. interposed therebetween. Inside these islands are P channel DSA structure MO8) transistor 20 and N
A channel DSA structure MOS transistor 21 is formed. 20 and 21 are drains 3. Channel part 4° source 5. Insulating film at gate part 6. Insulating film in field section7. Source electrode8. Gate electrode 9. Drain electrode 10.
Contact window 11. In addition to field plates 81 and 91, it also includes a buried layer 22 to reduce the so-called back gate effect. In the operating state, a channel 12 is formed in a region under the gate electrode 9 in contact with the insulating film 6, and electrical continuity is established between the source 5 and the drain 3, and a voltage is applied between the source 5 and the drain 3. A depletion layer 13 appears that supports the voltage.
さて、本発明の構造的な特徴は寄生バイポーラトランジ
スタのベースとなるチャネル部４中に生成再結合中心を
多量に含む領域又はバンドギャップが周囲の半導体領域
よシ広い領域又はこれらの効果を併せ持つ領域２３−を
形成することにある。Now, the structural feature of the present invention is that the channel portion 4, which is the base of the parasitic bipolar transistor, contains a region containing a large number of production recombination centers, a region with a wider band gap than the surrounding semiconductor region, or a region that has both of these effects. 23-.
以下、この領域の効果及びその実現方法について述べる
ものである。第３図は寄生バイポーラトランジスタがＮ
ＰＮ形の場合を例にとり、従来技術と本発明の効果をバ
ンド構造の点から明らかＫしたものである。これらの図
は説明を明確に行なうため、モデル的に表記されておシ
、寄生バイポーラトランジスタが動作する様々バイアス
が示され、破線Ｃ−−−）はフェルミレベルを、一点鎖
線は禁制帯の中心をそれぞれ表わしている。さて、従来
技術（第３図ａ）においては空乏層１３中で発生した正
孔及び電子（図中・及び０印で示す）がチャネル部４及
びドレイン３に流入する。流入した正孔がソース５とチ
ャネル部４の接合を順バイアスし、ソー２５からチャネ
ル部４へｈＦＩｎ倍の電子の注入を行なう。注入された
電子は空乏層１３中をすべり落ちる際、新たなキャリア
の発生をうながし、一種の正帰還作用をする。この過程
に前述の空乏層中の発熱が重なシ、素子の破壊モードに
入るものである。しかし、本発明（第３図ｂ）の如き構
造門実現すれば、空乏層１３中で発生した正゛孔及び電
子はそれぞれチャネル部４及び空乏層１３に流れ込むも
のの領域２３の禁制帯幅が広いためソース５と領域２３
の接合を注入が顕著になる程順バイアスすることはない
。また、充分、順ノ（イアスされたとしても領域２３中
に多量の生成再結合中心が存在するため、電子は領域２
３中で消、滅し、トランジスタ作用が生じない。発明者
らの実験によれば、チャネル部４中に領域２３を形成す
る方法としては絶縁物の禁制帯幅が広いこと、及びｓ１
巾に添加された異種元素が生成再結合中心と々ることを
応用し、酸素イ・オン、窒素イオン。The effects in this area and how to achieve them will be described below. Figure 3 shows that the parasitic bipolar transistor is N
Taking the case of the PN type as an example, the effects of the prior art and the present invention are clearly compared in terms of band structure. In order to make the explanation clear, these figures are expressed in model form to show the various biases at which the parasitic bipolar transistor operates. each represents. Now, in the prior art (FIG. 3a), holes and electrons (indicated by . and 0 marks in the figure) generated in the depletion layer 13 flow into the channel portion 4 and the drain 3. The inflowing holes forward bias the junction between the source 5 and the channel portion 4, and hFIn times as many electrons are injected from the source 25 into the channel portion 4. When the injected electrons slide down in the depletion layer 13, they promote the generation of new carriers, thereby acting as a kind of positive feedback. When this process is combined with the above-mentioned heat generation in the depletion layer, the device enters a destructive mode. However, if the structural gate of the present invention (FIG. 3b) is realized, holes and electrons generated in the depletion layer 13 flow into the channel part 4 and the depletion layer 13, respectively, but the forbidden band width of the region 23 is wide. For source 5 and area 23
The junction is not forward biased to the extent that the injection becomes significant. In addition, even if the electrons are sufficiently ordered, there are a large number of production and recombination centers in the region 23, so the electrons are
3, disappears and disappears, and no transistor action occurs. According to experiments conducted by the inventors, the method for forming the region 23 in the channel portion 4 requires that the forbidden band width of the insulator is wide and that s1
Oxygen ions, nitrogen ions, etc. are generated by applying the fact that different elements added to the width generate and reach recombination centers.
炭素イオン又はこれらの組み合せたものを添加すること
が有効であった。例えば１’８０にθＶで約５×１０Ｉ
４ｔＴｎ−２〜５ Ｘ Ｉ Ｏ”ｍ−２、これらの元素
をイオン注入した場合に寄生バイポーラトランジスタの
効果を小さくでき、特に酸素イオンをＩ Ｘ １０”ｃ
ｒｎ−”以上、注入した場合はその効果が顕゛著であっ
た。またＨｅ。Adding carbon ions or a combination thereof was effective. For example, at 1'80, approximately 5 x 10I at θV
4tTn-2~5XIO"m-2, when these elements are ion-implanted, the effect of the parasitic bipolar transistor can be reduced.
The effect was remarkable when more than rn-'' was injected.Also, He.
Ａｒ 、 Ｘｅ等不活性ガスを添加しても同様な効果が
認められた。しかし、この場合はアニールによって寄生
バイポーラ効果の抑制作用が小さくなったことから、Ｓ
ｉ と化合して絶縁物を形成しないような元素の添加は
前述の作用のうち、禁制帯幅の増加による注入の抑制効
果よシむしろ再結合中心の増加による注入された小数キ
ャリアの消滅が支配的と推察される。このような元素は
添加後のアニール条件を充分制御する必要があると考え
られる。Similar effects were observed even when inert gases such as Ar and Xe were added. However, in this case, because the suppressing effect on the parasitic bipolar effect was reduced by annealing, S
The addition of elements that do not combine with i to form an insulator has the effect of suppressing injection by increasing the forbidden band width, but rather by annihilating the injected minority carriers by increasing the number of recombination centers. It is assumed that this is the target. It is considered that it is necessary to sufficiently control the annealing conditions after addition of such elements.
本発明の別の形態としてチャネル部４及びソース５をｉ
結晶Ｓ工で形成することも実験的に試みた。これは多結
晶中では生成再結合中心が極めて多いことを利用したも
のである。この場合の素子製作条件はチャネル部４の接
合深さは約２μｍ１表面不純物濃度はＩ ＸＩＯｃｍ−
” ＋ソース５の接合深さは約ｌｐｍ ＋表面不純物濃
度は１．５ Ｘ １０（７）−３とし、島１８は３Ｘ１
０”％−ｓの不純物濃度とした。この場合には若干プロ
セス的に複雑となるものの寄生パイボ−２効果は全く認
められず、チャネル部４の占有面積が約１５０００ ｐ
ｒｎ”と太きいにもかかわらずドレイン３〜チャネル部
４内のリーク電流はμＡ、以下のオーダでおるという良
好な結果を得た。尚、ここではソースまで多結晶を用い
たが、これは実験の都合によるものでオシ、必ずしも必
要としない。父、空乏層の延びるドレイン領域が多結晶
の場合は空乏層が延びず高耐圧特性の実現が国難であっ
た。従って、ドレイン領域は多結晶であってはいけない
。尚、ＤＳＡ構造のＭＯＳ ）ランジスタに本発明を適
用する場合、領域２３が絶縁物化する程、Ｎ、０等の元
素を添加することは得策で々いことに注意が必要である
。これは領域２３が絶縁物化するとドレイン３〜ソース
５間にかかる電圧を、この領域２３で支えなければなら
ない場合が生じ、イオン注入量の増大が不可欠となるか
らである。説明からも明らかなように、注入量は絶縁物
化する場合に比べて、１桁から３桁程度小さくできるこ
と・に本発明の効果の特長がある。また領域２３は寄生
バイポーラトランジスタのエミッタを全て囲む形で形成
することは必ずしも必要でない。この理由は第３図にお
いてソース５から横方向に注入されて島１８に到達する
キャリアは、不純物ＩｆＯ比が小さいため少ないこと、
及び島１日に到達するまでの距離（ベース幅）が長いた
め再結合して消滅し易く、バイポーラトランジスタとし
ての動作にあまり寄与しないためである。In another embodiment of the present invention, the channel portion 4 and the source 5 are
We also experimentally attempted to form it using crystal S technology. This takes advantage of the fact that polycrystals have an extremely large number of production and recombination centers. The device manufacturing conditions in this case are that the junction depth of the channel portion 4 is approximately 2 μm, the surface impurity concentration is I
” + The junction depth of the source 5 is approximately lpm + The surface impurity concentration is 1.5 x 10(7)-3, and the island 18 is 3 x 1
The impurity concentration was set to 0''%-s. In this case, although the process was somewhat complicated, no parasitic pibo-2 effect was observed, and the area occupied by the channel portion 4 was approximately 15,000 p.
We obtained good results in that the leakage current in the drain 3 to channel part 4 was on the order of μA or less despite the large size. This is due to the convenience of the experiment and is not necessarily necessary.If the drain region where the depletion layer extends is polycrystalline, the depletion layer will not extend and achieving high breakdown voltage characteristics has been a national problem.Therefore, the drain region should be polycrystalline. Note that when applying the present invention to a DSA structure MOS transistor, it is not advisable to add elements such as N and 0 to the extent that the region 23 becomes an insulator. This is because if the region 23 is made of an insulator, the voltage applied between the drain 3 and the source 5 may have to be supported by this region 23, and an increase in the amount of ion implantation becomes essential. As is clear, the advantageous effect of the present invention is that the implantation amount can be reduced by one to three orders of magnitude compared to the case of using an insulator.Also, the region 23 is formed to completely surround the emitter of the parasitic bipolar transistor. The reason for this is that in FIG. 3, fewer carriers are injected laterally from the source 5 and reach the island 18 because the impurity IfO ratio is small.
This is also because the distance (base width) it takes to reach the island is long, so it is easy to recombine and disappear, and it does not contribute much to the operation as a bipolar transistor.
なお領域２３としては作用性が高い箇所に設けることが
必要である。第２図の場合においては、寄生バイポーラ
トランジスタがパーティカル構造なので、実効のベース
幅が狭く、かつエミッタとベースの濃度比が大きいエミ
ッタ直下に設けることが必要である。Note that the region 23 needs to be provided at a location with high effectiveness. In the case of FIG. 2, since the parasitic bipolar transistor has a particle structure, it is necessary to provide it directly under the emitter, which has a narrow effective base width and a high concentration ratio between emitter and base.
次に、本発明の別の応用例について述べる。第４図はπ
形の単結晶基板１中に複数の相補形ＭＯＳトランジスタ
を形成したものであり、Ｎチャネルトランジスタ２１は
基板中に直接形成されるが、Ｐチャネルトランジスタ２
０は基板１中にウェル２４と呼ばれる領域（この例では
Ｎ形とした）を形成し、この中に製作されている。これ
らの素子は占有面積を小さくするため、周囲を囲む絶縁
分離領域２５を設けて、相互の距離を可能なＩＩＪ！シ
接近させることが試みられている。しかし、ある限度を
超えて接近させると、例えばＰチャネルＭＯＳトランジ
スタ２０のドレイン（ｐ形）、ウェル（Ｎ形）＃基板（
７ＣｉＰ形）、２１のドレイン（Ｎ形）から構成される
寄生ＰＮＰＮ素子が電源投入時などにオンル、Ｐチャネ
ルＭＯＢ ）ランジスタ２０のドレインとＮチャネルＭ
ＯＥ＋ トランジスタ２１のソース金電気的に導通させ
てしまういわゆるラッチアップが生ずる。ＰＮＰＮ素子
はＰＩＦ ）ランジスタとＮＰＮ ）ランジスタが正帰
還ループを構成したものであるが、本発明の特徴である
、生成再結合中心を多量に・含む領域、又はノくンドギ
ャップが周囲の半導体領域よ如広い領域またはこれらの
効果を併せ持つ領域２３をこの素子の電流通路中に設け
れば、少なくとも一方のトランジスタが充分な正帰還量
を、他方のトランジスタに与えることができなくなシ、
前述のラッチアップは牢じ力いことは明白である。第４
図においては領域２３を酸素のイオン注入で形成した場
合の例を示している。Next, another application example of the present invention will be described. Figure 4 is π
A plurality of complementary MOS transistors are formed in a shaped single-crystal substrate 1, and an N-channel transistor 21 is formed directly in the substrate, but a P-channel transistor 2 is formed directly in the substrate.
0 forms a region called a well 24 (in this example, it is N-type) in the substrate 1, and is manufactured therein. In order to reduce the area occupied by these elements, an insulating isolation region 25 surrounding them is provided to minimize the distance between them. Attempts are being made to bring them closer together. However, if they are brought close to each other beyond a certain limit, for example, the drain (p type) of the P channel MOS transistor 20, the well (n type) #substrate (
When the power is turned on, etc., a parasitic PNPN element consisting of the drain of transistor 20 (N-type) and the drain of transistor 20 (P-channel MOB) and the drain of N-channel M
A so-called latch-up occurs which causes the source metal of OE+ transistor 21 to become electrically conductive. A PNPN element consists of a PIF transistor and an NPN transistor that form a positive feedback loop, and the feature of the present invention is that it can be used in a region containing a large number of production-recombination centers or in a semiconductor region with a non-kund gap surrounding it. If a very wide region or a region 23 having both of these effects is provided in the current path of this element, at least one transistor will not be able to provide a sufficient amount of positive feedback to the other transistor.
It is clear that the aforementioned latch-up is irresistible. Fourth
The figure shows an example where the region 23 is formed by oxygen ion implantation.
この場合、ＰＮＰ）ランジスタのベース中に領域２３が
形成されたこととなる。このような構造とすれは、寄生
Ｐ Ｎ Ｐ、Ｎ素子が動−作しないため、相補形のＭＯ
日トランジスタをパターンルールが許容する極限まで高
集積化することが可能となる。In this case, a region 23 is formed in the base of the PNP transistor. With such a structure, the parasitic PNP,N elements do not operate, so the complementary MO
It becomes possible to highly integrate transistors to the maximum extent permitted by pattern rules.
次に、本発明の第２の応用例について述及ることとする
。第２図においては誘電体分離された島（１８及び１９
）に−個ずつの素子が形成されているが、本発明の応用
例を組み合せ、バイポーラトランジスタ及びＭＯＳ ト
ランジスタ等の高耐圧素子を１つの島に収容すると共に
、島１８又は１９中には第４図に示したよりな形で複数
の素子を搭載することが可能でるる。この場合、第４図
の基板ｌは第２図の島１８又は１９に対応することとな
る。このような構成とすれは、高耐圧のバイポーラトラ
ンジスタ又は高耐圧のＭＯＳ ）ランジスタと多数の低
耐圧の０ＭＯ８からなる回路を同一基板上に形成できる
ことは明白であり、高耐圧素子を含む回路の集積度向上
による経済化が、本発明の利点として追加される。Next, a second application example of the present invention will be described. In Figure 2, dielectrically isolated islands (18 and 19)
), but by combining the applied examples of the present invention, high voltage elements such as bipolar transistors and MOS transistors are accommodated in one island, and a fourth element is formed in island 18 or 19. It is possible to mount multiple elements in the form shown in the figure. In this case, the substrate l in FIG. 4 would correspond to the island 18 or 19 in FIG. 2. With such a configuration, it is obvious that a circuit consisting of a high voltage bipolar transistor or a high voltage MOS transistor and a large number of low voltage 0MO8 transistors can be formed on the same substrate, and it is possible to integrate circuits including high voltage elements. Economies due to increased efficiency are additional advantages of the present invention.
なお上記の実施例においてはＤＳ＾構造のＭＯＢ ）ラ
ンジスタ及び０ＭＯ８）ランジスタの場合について述べ
たが、この外にラテラル構造のＭＯＥＩ ）ランジスタ
についても、適用できることは云うまでもない。In the above embodiments, the MOB transistor and the MOEI transistor having a DS^ structure have been described, but it goes without saying that the present invention can also be applied to a MOEI transistor having a lateral structure.
（発明の効果）
以上、説明したように、本発明の提案する領域を組み込
んだＭＯＢ形の半導体装置は寄生バイポーラ効果を小さ
くできるため、素子の熱暴走がなく高耐圧特性の実現に
有利となる。又、低耐圧素子の高集積化にも極めて効果
的である。(Effects of the Invention) As explained above, since the MOB type semiconductor device incorporating the region proposed by the present invention can reduce the parasitic bipolar effect, there is no thermal runaway of the element and it is advantageous in realizing high breakdown voltage characteristics. . Furthermore, it is extremely effective for increasing the degree of integration of low-voltage elements.
第１図は従来の半導体装置の断面図、第２図及び第４図
は本発明の半導体装置の一実施例、第３図は本発明の効
果を模式的に示したエネルギーバンド図である。
ｌ・・支持基板、２・・ＤＳＡ構造のＭＯＢ トランジ
スタ、３・・・ドレイン、４・・・チャネル部、５・・
・ソース、６・・・ゲート部の絶縁膜、７・・・フィー
ルド部の絶縁膜、８・・ソース電極、ａｌ・・・ソース
フィールドプレート、９・・ゲート電極、９１川ゲート
フイールドプレート、１０−・・ドレイン電極、１１・
・・コンタクト窓、１２−：チャネル、１３・・空乏層
、１４・・正孔、１５・・・電子、１６・・・支持基板
、１７・・分離膜、１Ｂ・・・Ｐ形の島、１９・・・Ｎ
形の島、２０・・・ＰチャネルのＭＯＢ ）ランジスタ
、２１・・・ＮチャネルのＭＯＢ ）ランジスタ、２２
・・埋込層、２３・・生成再結合中心を多量に含む領域
又はバンドギャップが周囲の半導体領域よシ広い領域又
はこれらの効果を併せ持つ領域、２４・・・ウェル、２
５・・絶縁分離領域
％杵出願人
第１図
第２図
第３図
第４図
コFIG. 1 is a sectional view of a conventional semiconductor device, FIGS. 2 and 4 are examples of the semiconductor device of the present invention, and FIG. 3 is an energy band diagram schematically showing the effects of the present invention. l...Support substrate, 2...MOB transistor with DSA structure, 3...Drain, 4...Channel part, 5...
- Source, 6... Insulating film of gate part, 7... Insulating film of field part, 8... Source electrode, al... Source field plate, 9... Gate electrode, 91 River gate field plate, 10 -...Drain electrode, 11.
... Contact window, 12-: Channel, 13... Depletion layer, 14... Hole, 15... Electron, 16... Support substrate, 17... Separation film, 1B... P-type island, 19...N
shaped island, 20...P channel MOB) transistor, 21...N channel MOB) transistor, 22
...Buried layer, 23...A region containing a large amount of production recombination centers or a region whose band gap is wider than the surrounding semiconductor region, or a region having both of these effects, 24...Well, 2
5. Insulation separation area % Punch Applicant Figure 1 Figure 2 Figure 3 Figure 4
Claims (1)
、寄生パイボーラトランノスタのベース領域に、生成再
結合中心を含む領域又はバンドギャップが周囲の半導体
領域に比べて広い領域が少なくとも形成されたことを特
徴とする半導体装置。 （２） ＭＯ８形トランジスタを含む半導体装置におい
て少なくとも寄生バイポーラトランジスタのベース領域
に多結晶８１層を含むことを特徴とする特許請求の範囲
第１項記載の半導体装置。 （３）複数の誘電体分離された島を有し、骸晶の少なく
とも１つには高耐圧素子が形成されておシ、かつ、骸晶
の少なくとも１つには、寄生バイポーラトランジスタを
形成するベース領域に、生成再結合中心を含む領域また
はバンドギャップが周囲の半導体領域に比べて広い領域
が形成されている素子を含むことを特徴とする特許請求
の範囲第１項記載の半導体装置。[Claims] (11) In a semiconductor device including an MOB transistor, at least a region containing a production recombination center or a region having a wider band gap than the surrounding semiconductor region is formed in the base region of the parasitic pibora transnoster. (2) The semiconductor device according to claim 1, characterized in that the semiconductor device includes an MO8 transistor, and includes a polycrystalline 81 layer at least in the base region of the parasitic bipolar transistor. (3) It has a plurality of dielectrically separated islands, a high voltage element is formed in at least one of the skeleton crystals, and a parasitic bipolar transistor is formed in at least one of the skeleton crystals. 2. The semiconductor device according to claim 1, wherein the semiconductor device includes an element in which a region including a production-recombination center or a region having a wider band gap than surrounding semiconductor regions is formed in a base region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59045666A JPS60189967A (en) | 1984-03-12 | 1984-03-12 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59045666A JPS60189967A (en) | 1984-03-12 | 1984-03-12 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60189967A true JPS60189967A (en) | 1985-09-27 |
Family
ID=12725706
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59045666A Pending JPS60189967A (en) | 1984-03-12 | 1984-03-12 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60189967A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1999017373A1 (en) * | 1997-09-30 | 1999-04-08 | Infineon Technologies Ag | Semiconductor power component with enhanced latch-up resistance |
| FR2940525A1 (en) * | 2008-12-18 | 2010-06-25 | Commissariat Energie Atomique | SEMICONDUCTOR DEVICE |
-
1984
- 1984-03-12 JP JP59045666A patent/JPS60189967A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1999017373A1 (en) * | 1997-09-30 | 1999-04-08 | Infineon Technologies Ag | Semiconductor power component with enhanced latch-up resistance |
| FR2940525A1 (en) * | 2008-12-18 | 2010-06-25 | Commissariat Energie Atomique | SEMICONDUCTOR DEVICE |
| EP2200083A3 (en) * | 2008-12-18 | 2012-04-04 | Commissariat À L'Énergie Atomique Et Aux Énergies Alternatives | Semiconductor detector comprising floating gate |
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