JPS6018938A - Case for semiconductor device - Google Patents
Case for semiconductor deviceInfo
- Publication number
- JPS6018938A JPS6018938A JP58127251A JP12725183A JPS6018938A JP S6018938 A JPS6018938 A JP S6018938A JP 58127251 A JP58127251 A JP 58127251A JP 12725183 A JP12725183 A JP 12725183A JP S6018938 A JPS6018938 A JP S6018938A
- Authority
- JP
- Japan
- Prior art keywords
- sealing
- cap
- bonding
- substrate
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/162—Disposition
- H01L2924/16251—Connecting to an item not being a semiconductor or solid-state body, e.g. cap-to-substrate
Abstract
Description
【発明の詳細な説明】
〔発明の属する技術分野〕
本発明は半導体装置用ケースに関し、特に接着剤が施さ
れたセラミックキャップにょシ封止金行うセラミックケ
ースの構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a case for a semiconductor device, and more particularly to the structure of a ceramic case in which a ceramic cap coated with an adhesive is sealed with a sealing metal.
第１図は従来一般に使用されているセラミックケースを
用いた半導体装置の断面図である。FIG. 1 is a sectional view of a semiconductor device using a conventionally commonly used ceramic case.
第１図において、１はアルミナ等のセラミック絶縁材料
よりなるセラミックケース基板であシ、セラミックケー
ス基板１上には半導体素子の接続用金属電極層２および
配線用の金属層２′が形成され、金属電極層２上には金
等のンルダー３を使用し半導体素子４が接着される。一
方配線用の金属電極層は合金よりなる外部リード５に接
続されている。半導体素子４と配線用金属電極層の接続
は金等のボンディング細線６により行なわれる。In FIG. 1, 1 is a ceramic case substrate made of a ceramic insulating material such as alumina, and on the ceramic case substrate 1 are formed a metal electrode layer 2 for connecting semiconductor elements and a metal layer 2' for wiring. A semiconductor element 4 is bonded onto the metal electrode layer 2 using a glue 3 made of gold or the like. On the other hand, a metal electrode layer for wiring is connected to an external lead 5 made of an alloy. The connection between the semiconductor element 4 and the metal electrode layer for wiring is made by a thin bonding wire 6 made of gold or the like.
接続完了後、外部よシの影響を肋ぐため鉛ガラス８等の
低融点ガラスによシセラミックキャップとセラミックケ
ース基板ｌは接着されセラミックケースに封止された半
導体装置は完成する。After the connection is completed, the ceramic cap and the ceramic case substrate l are bonded with a low melting point glass such as lead glass 8 to protect against the influence of external elements, and the semiconductor device sealed in the ceramic case is completed.
し）・るに、上記した金属電極層形成領域と封止用キャ
ップ接着領域が同一面に形成されている従来の半導体装
置用セラミックケースでは封止時、約５００Ｃ程度の高
温雰囲気中で、キャップ頭部を加圧しながら行なわれる
ため封着用の低融点ガラス８が溶は出し金属層２′に接
続した金のポンディング細線上へ流れ込む現象が起る。However, in the conventional ceramic case for semiconductor devices in which the metal electrode layer forming area and the sealing cap adhesion area are formed on the same surface, the cap is attached in a high temperature atmosphere of approximately 500C during sealing. Since this is carried out while applying pressure to the head, a phenomenon occurs in which the low melting point glass 8 for sealing melts and flows onto the gold bonding thin wire connected to the metal layer 2'.
しかるときは金線に水平方向の力が加わり、接続個所よ
シ金線をはがしたシ、根元よシ切ったシする現象が起シ
、半導体装置を不良にしてしまうという欠点があった。When this happens, a horizontal force is applied to the gold wire, causing the wire to be peeled off at the connection point or cut at the base, resulting in a defective semiconductor device.
本発明の目的は、上記欠点を除去し、封止材料によるボ
ンディング細線の断線やはがれを起すことなく、かつ封
止効果の大きい半導体装置用ケースを提供することにあ
る。SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks, to provide a case for a semiconductor device that does not cause disconnection or peeling of thin bonding wires due to the sealing material, and has a large sealing effect.
本発明の半導体装置用ケースは、セラミックケース基板
上に外部リードと接続される金属電極層形成領域と封止
用キャップを接着する領域を有する半導体装置用ケース
において、前記セラミックケース基板上の金属電極層形
成領域と封止用キャップの接着領域とが異なる平面に形
成されることによシ構成される。The semiconductor device case of the present invention has a metal electrode layer forming region connected to an external lead on a ceramic case substrate and a region to which a sealing cap is bonded. The structure is such that the layer forming region and the adhesive region of the sealing cap are formed on different planes.
以下本発明の実施例について図面を参照して詳細に説明
する。Embodiments of the present invention will be described in detail below with reference to the drawings.
第２図は本発明の一実施例のセラミックケース基板の断
面図である。FIG. 2 is a sectional view of a ceramic case substrate according to an embodiment of the present invention.
図に示すようにセラミックケース基板１１は全体として
凸形構造をなし、その頂部Ａ部には金属電極層１２及び
１２′が形成され配線用金属電極層１２’は合金よシな
る外部リード１５に接続され、また対土用キャップを接
続する領域である低い個所Ｂ部を有している。すなわち
金属電極形成領域であるＡ部と封止用キャップの接着領
域であるＢ部とは異なる平面に形成されている。As shown in the figure, the ceramic case substrate 11 has a convex structure as a whole, and metal electrode layers 12 and 12' are formed on the top part A, and the wiring metal electrode layer 12' is connected to an external lead 15 made of alloy. It has a low part B which is a region where the soil cap is connected. That is, part A, which is the metal electrode forming region, and part B, which is the bonding region of the sealing cap, are formed on different planes.
第３図は本発明の一実施例を使用して組立てた半導体装
置の断面図である。FIG. 3 is a cross-sectional view of a semiconductor device assembled using an embodiment of the present invention.
図において１１，１２．１２’、１５よりなる部分は第
２図に示した本発明の主要部でヤ９、これにンルダー１
３によシ半導体素子１４が接着され、半導体素子のポン
ディングパッドと配線用金属電極層１２’はボンディン
グ線１６により接続されている。この組立体には制止用
キャップ１７がかむせられ封着用の低融点ガラス１８で
封止される。封止する際高温雰囲気でキャップを加圧し
ながら封止するが、セラミックケースの封止部が凸状の
低い個所（Ｂ部）に設けられ、こ＼で封止されるので低
融点ガラス１８はＡ部のボンディング結線を飾した金員
電極層に到達しない。そのためボンディング細線を切っ
たυ、又ははがしたシすることはなくなる。In the figure, the parts 11, 12, 12', and 15 are the main parts of the present invention shown in FIG.
A semiconductor element 14 is bonded to the substrate 3, and the bonding pad of the semiconductor element and the wiring metal electrode layer 12' are connected by a bonding wire 16. This assembly is fitted with a stop cap 17 and sealed with low melting point glass 18 for sealing. When sealing, the cap is pressurized in a high-temperature atmosphere, and the sealing part of the ceramic case is provided at a low convex part (part B), and the low melting point glass 18 is sealed here. It does not reach the metal electrode layer decorating the bonding connection in part A. Therefore, there is no need to cut or peel off the thin bonding wire.
また第３図に示したようにセラミックケース基板１１と
セラミックキャップ１７のすきまを狭くすれば、ガラス
がこのすきまに吸い込まれ、封止面積を大きくすること
ができるので封止渇果をよシ向上させることができる。Furthermore, as shown in Fig. 3, if the gap between the ceramic case substrate 11 and the ceramic cap 17 is narrowed, the glass will be sucked into this gap and the sealing area can be increased, which will improve sealing efficiency. can be done.
以上説明したとおり、本発明によれば、半導体装置のボ
ンディング線が切れたシ、はがれたシすることなく、又
封止効果も向上し、半導体装置の品質、歩留まシを大幅
に改善することができる。As explained above, according to the present invention, the bonding lines of semiconductor devices do not break or peel, and the sealing effect is improved, and the quality and yield of semiconductor devices are significantly improved. be able to.
第１図は従来の半導体装置用ケースを用いた半導体装置
の断面図、第２図は本発明の一実施例のセラミックケー
ス基板の断面図、第３図は本発明の一実施例を使用して
組立てた半導体装置の断面図である。
１．１１・・・・−・セラミックケース基板、２．２’
。
１２．１２’・・・・・・金属電極層、３，１３・・・
・・・ンルダー、４．１４・・・・・−半導体素子、５
．ｉ５・・・−・・外部リード、６，１６・・・・・−
ボンディング細線、７゜１７・・・・・・封止用キャッ
プ、８．１８・・・・・・低融点ガラス（鉛ガラス）、
Ａ・−・・・−金属電極層形成面、Ｂ・・・・・・接着
封止面。
′″４−１ 口
茅２図
茅３回
１６５−FIG. 1 is a sectional view of a semiconductor device using a conventional semiconductor device case, FIG. 2 is a sectional view of a ceramic case substrate according to an embodiment of the present invention, and FIG. 3 is a sectional view of a semiconductor device using an embodiment of the present invention. FIG. 1.11... Ceramic case board, 2.2'
. 12.12'...metal electrode layer, 3,13...
...unruder, 4.14...-semiconductor element, 5
．． i5...--External lead, 6, 16...-
Bonding thin wire, 7゜17...Sealing cap, 8.18...Low melting point glass (lead glass),
A.---Metal electrode layer forming surface, B...Adhesive sealing surface. '''4-1 Kuchika 2 illustrations Kaya 3 times 165-
Claims (1)
電極層形成領域と封止用キャップを接着する領域を有す
る半導体装置用ケースにおいて、前記セラミックケース
基板上の金属電極層形成領域と封止用キャップの接着領
域とが異なる平面に形成さり、ていることを特徴とする
半導体装置用ケース。In a semiconductor device case having a metal electrode layer forming area connected to an external lead and a sealing cap bonding area on a ceramic case substrate, the metal electrode layer forming area on the ceramic case substrate and a sealing cap bonding area are provided. A case for a semiconductor device, characterized in that an adhesive area is formed on a different plane.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58127251A JPS6018938A (en) | 1983-07-13 | 1983-07-13 | Case for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58127251A JPS6018938A (en) | 1983-07-13 | 1983-07-13 | Case for semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6018938A true JPS6018938A (en) | 1985-01-31 |
Family
ID=14955425
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58127251A Pending JPS6018938A (en) | 1983-07-13 | 1983-07-13 | Case for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6018938A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5107214A (en) * | 1989-03-09 | 1992-04-21 | Nippon Steel Corporation | Hot flaw detector with annular injection port for injecting cooling liquid |
-
1983
- 1983-07-13 JP JP58127251A patent/JPS6018938A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5107214A (en) * | 1989-03-09 | 1992-04-21 | Nippon Steel Corporation | Hot flaw detector with annular injection port for injecting cooling liquid |
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