JPS60189058A - Multiprocessor system - Google Patents

Abstract

PURPOSE:To allow a main CPU to execute the abnormality processing routine of a slave CPU accurately all the time by detecting abnormality by an abnormality detecting circuit if the abnormality occurs in a cycle wherein the slave CPU occupies a main bus. CONSTITUTION:If the abnormality occurs in the cycle wherein the slave CPU2 occupies the main bus 7, the abnormality detecting circuit 3 detects the abnormality; and then the state of the bus 7 at the time of the error occurrence is latched in an ECR register 22 with a signal 36. The circuit 3 sets the main bus occupation rate of the CPU2 to 0 through a signal 37 and a BMR register 6 and also inputs a signal 38 to an interruption generating circuit 4. Then, the circuit 4 inputs an interruption signal 35 to an MCR register 21 and the main CPU1, when is released from hold simultaneously with the abnormality detection. Consequently, the CPU1 accepts an interruption request and executes the abnormality processing routine of the CPU2 accurately all the time on the basis of the information held in the register 22.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention (c) relates to a multiprocessor system, and more specifically, a slave central processing unit (hereinafter abbreviated as CPU).
This invention relates to a multiprocessor system in which the main CPU accurately executes an abnormality processing routine regarding a slave CPH whenever an abnormality occurs in a cycle in which a slave CPH occupies the main bus.

(Prior Art) In a conventional multiprocessor system consisting of a main CPU and a slave CPU, if some abnormality is detected during a cycle in which the slave CPU is using the main bus, an interrupt is generated and the main CPU interrupts the slave CPU. A CPU error handling routine was being executed.

However, in this case, even if an abnormality is detected and an attempt is made to jump to the abnormality handling routine, if the main CPU itself is halted and its operation has stopped, the main CPU
The error handling routine itself cannot be executed.

Also, of course, since there was an abnormality, the slave CPU could not execute the process. Therefore, both the main and slave units become inoperable, and the entire system becomes inoperable.

(Objective) It is an object of the present invention to provide a device that eliminates the above-mentioned drawbacks and allows the main CPH to always accurately execute an abnormality processing routine when an abnormality is detected during the cycle of a slave CPU in a multiprocessor system. do.

(Embodiment) In the present invention, when an abnormality occurs in a cycle in which the slave CPU occupies the main bus, the abnormality detection circuit detects the abnormality and further operates the registers controlling the main C and PU. , set the main bus occupancy rate of the slave CPU to 0
Then, the main CPU reliably executes and configures the slave CPH's abnormality processing routine.

For example, the present invention can be applied to a slave OP on the main bus.
A main bus occupancy setting register is provided to store a variable value for determining the TT occupancy, and the main CPU and slave CPU are selectively connected to or disconnected from the main bus. 6 multiplexer, a function to detect that an abnormality has occurred on the main bus, a function to latch the state at the time of the abnormality in the recovery processing register when an abnormality is detected, and a function to set the main bus occupancy rate at the same time. an abnormality detection circuit having a function of clearing a register and a function of inputting a trigger signal to an interrupt generation circuit for generating an interrupt to the main CPU; and an abnormality detection circuit connected to the main bus to control the main CPU. Furthermore, there is a main CPU control register which is cleared by a signal from the interrupt generation circuit, and a main CPU control register which is connected to the main bus and which is connected to the slave (3P) register.
It consists of a slave CPU control register that controls U.

FIG. 1 is a block diagram schematically showing one embodiment of the present invention. Main CPU1 and slave 0PU2 are selectively connected to main bus 7 by bus multiplexer 5.
disconnected. In addition, the proportion of the main bus 7 occupied by the slave CPU 2 is determined by a bus multiplexer ratio (hereinafter abbreviated as BMR) register B. This BMR register 6 is used to optimize the occupancy rate of the main bus 7. For example, when the load on the main 0PU1 is large and the load on the slave CPU2 is small, the value of the BMR register is decreased (in other words, the occupancy rate of the main 0PU1 on the main bus 7 is increased and the occupancy rate of the slave C!PU2 is decreased). ) Main C! This allows the synchronization of processing between PU1 and slave CPU2 to be interrupted.

The abnormality detection circuit 3 detects an abnormality on the main bus 7 and sends a trigger signal 66 to an error code register (hereinafter referred to as F).
It is abbreviated as OR register. )22 and EOR register 2.
2 to latch the abnormal state of the bus. EC
The R register 22 uses the signal 62 to latch an abnormal state.

The main processor control register (hereinafter abbreviated as MCR register) 21 controls the main processor control register by a signal 34.
This is for direct control of U1. To explain further, the main CPU 1 is connected to the main CPU 1 on the main bus 7.
The contents of the MOR register 21 are manipulated using the PU control signal 31, and the main c'p is
The ui is controlled. 1 cymain 0PU1 is M
I am controlling myself through O'E Regisc 21. In addition, the slave processor control register (hereinafter abbreviated as SC'R register) 26 receives the slave C! This is a register that controls PU2, and its contents (main CPU1 is connected to main bus 7).
In addition, the interrupt generation circuit 4 inputs the interrupt generation signal 35 to the MOR register 21 and the main 0PU1 in response to the signal 38 from the abnormality detection circuit 3.
, and further generates an interrupt to the main CPU 1. Further, the memory 8 is a shared memory between the main CPU 1 and the slave CPU 2, which is connected to the main bus 7.

Next, the operation of the present invention will be explained using FIG.

First, when an abnormality occurs in a cycle in which the slave cPu2 occupies the main bus 7, the abnormality detection circuit detects it and uses a signal 36 to instruct the ECP register 22 to latch the state of the bus at the time of the error occurrence. Therefore,
Tf: The CR register 22 uses the signal 52 to latch the state of the main bus 7 when an error occurs. At the same time, the abnormality detection circuit 5 issues a signal 67 to clear the EMR register 6, and further inputs a signal 38 to the interrupt generation circuit 4. Here, if the BM only register 6 is cleared, the main bus occupancy rate of the slave CPU 2 becomes 0, so the main bus 7 becomes completely the main 0P from then on.
It will be occupied by U1.

Further, the interrupt generation circuit 4 receives the signal 68 and sends the interrupt generation signal 35 to the MOR register 21 and the main CPU.
Input to U1. Therefore, the MCRL/register 21 will be cleared and the main 0PU1 will be interrupted. Here, before s 14% occurs, the main C! If the PU1 uses the main bus 7 and the main CPU control signal 31 to set a flag in the MOR register 2101 bit and bold itself, the interrupt generation signal 35 from the interrupt generation circuit 4 causes the PU1 to
Since the R register 21 is cleared, the halt that was previously placed on the main CPU 1 is canceled along with the abnormality detection.

As mentioned above, since the main 0PU1 is released from the halt state, it accepts the interrupt request mentioned earlier and uses the information held in the EC'B register 22 to respond to the bus cycle of the slave 0PU2. It is possible to perform work to remove any abnormalities that have occurred.

Also, in this recovery process, if necessary, main 0PU1
is connected to the SCR register 26 via the main bus 7 and signal 33.
Flag the 01 bit so that the slave CPU
2 can be initialized.

(Effects) As explained above, in the present invention, when an abnormality occurs in a cycle in which the slave CPU occupies the main bus, the abnormality detection circuit detects the abnormality, and then the slave CPU
The main bus occupancy rate of C is set to 0, and the interrupt generation circuit activated by the abnormality detection circuit is
It is configured to clear the main cPU control register that controls the PU and interrupt the main CPU.

Therefore, according to the present invention, if an abnormality is detected in a cycle in which the slave CPU occupies the main bus, even if the main CPU is halted and the main CPU is in a stopped state, After removing the waste, main C! Since a PUK interrupt is issued, the main CPU in the above case is exactly connected to the slave CPU.
Since the main CPU can execute the abnormality processing routine without being restricted by the abnormality of the slave CPH, the 4S reliability of the entire system can be greatly improved.

Also, in the above, one main CPU and one slave C
Although the explanation has been given using a system consisting of one main CPU and two main CPUs as an example, the present invention is limited to this.
One or more slaves c 'p U.

Or two or more main CPUs and one slave CPU
It is also applicable to a system consisting of U.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram of one embodiment of the present invention. , 1... Main cPU 2...Slave CPU 3... Abnormality detection circuit 4...Interrupt generation circuit 5...Bus multiplexer 6...FMF register that's all Applicant: Epson Corporation Suwa Seikosha Co., Ltd.

Claims (1)

[Claims] means for detecting an abnormality occurring in a cycle in which a slave central processing unit occupies a main bus; means for thereafter operating a device that controls the main central processing unit; and a means for reducing the main bus occupancy rate of the slave central processing unit to zero A multiprocessor system characterized by comprising an abnormality detection circuit having means for detecting an abnormality.