JPS60187994A - Memory circuit - Google Patents

Abstract

PURPOSE:To reduce the constitution area of a memory cell by arranging MOS transistors (TRs) at intersections between address lines and memory cell output lines. CONSTITUTION:In the memory cell formed with TRs Q3-Q6 having address lines A1 and A2 and word lines W1, anti-W1, W2, and anti-W2 corresponding to these address lines, N type MOS TRs Q1 and Q8 are turned on when the address line A1 is selected and goes to the high level. In this case, the address line A2 is in the low level, and P type MOS TRs Q9 and Q11 at intersections between lines A1 and A2 and memory output lines which do not correspond to these lines are turned on, and lines W1 and anti-W1 are connected electrically. When the line A2 is selected, lines W2 and anti-W2 are connected electrically similarly. P type MOS TRs Q9-Q11 arranged at intersections between address lines and data output lines to the other word lines which do not correspond to address lines are equivalent to metallic wirings, and thus, the constitution area of the memory cell is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a memory circuit in which memory cells each having a plurality of address lines and word lines are configured using CMOS silicon gate transistors.

(Prior Art) Conventionally, a memory circuit in which each memory cell has two address lines and two word lines is configured as shown in the circuit diagram of FIG. In the figure, Q1+Q2, Q41Q6~
Q8 is an N-type MOS transistor, Qa and Qs are P-type M
OS transistor %Al, A2 is the first. The address line vvhw2 for selecting the second memory cell is the first. The positive phase word line of the second memory cell, Wl.

W2 is a reverse phase word combination of the first and second memory cells.

MOS transistors Q3 to Q6 constitute one memory cell, and MOS transistors Q3.
Output a of Q411111 or MOS) transistor Q5. The output on the Qa side is the address line A1. Selected by A2. That is, the outputs a and b of the memory cells whose MOS transistors Qt and Qs are active are connected to the word mwll -Vvl by the address line A1, and the outputs of the MOS transistors Q2 . Q7 becomes active, and the outputs a and b of the memory cells are connected to word lines W2. It is output to W2.

The structure of a mask pattern of an integrated circuit (IC) in which this memory circuit is constructed of CMOS silicon gate transistors is shown in FIG. This wiring pattern has three types: metal wiring 10, polycrystalline silicon (gate polysilicon) wiring #i11, and diffusion layer wiring 12.These are distinguished by dot spinning, single dot chain wiring, and real axis, respectively. . Note that the X marks indicate the contacts 13 of these wirings.

Normally, as shown in the figure, the outputs a and b of the memory cell are drawn out from the connection point of the source and drain of the transistors Q3, Q4 or Qs+Q6, so diffusions 110 are used. 0 point of line W1 or W
In order to connect to point f of l, polycrystalline silicon wiring 11
It intersects with the address line At+A2 composed of Here, since this mask pattern groove diagram is composed of silicon gate MOS transistors, its manufacturing method is the self-aligned gate method (5elf@ali
gned-gate) is used. Therefore, an N-type channel is formed at the intersection (X-marked point) between the output diffusion layer 04 of the memory cell and the polycrystalline silicon arrangement 11 of the address line A1, and MOS transistors Qt and Qs are formed.

However, since a channel is formed at the intersection of the address line A2 with the polycrystalline silicon wiring 11, an electrical disconnection occurs at that point, and the transistor Q1. Qs and outputs a and b of the memory cell are not connected.

Therefore, regarding the intersection of 7, the Horisilicon payout is 1.
It is necessary to avoid the formation of a channel by changing the wiring line 12 or diffusion layer wiring 12 to a metal paulownia wiring line 10 and connecting it. In this figure, the diffusion 1-fM12 is changed to a gold striped wiring 10 between the contact g''ni'J + the contact m-n.For this reason, 9 memory cells with many contact parts=m are formed. This increases the area between contacts 1-1 and t-1 in FIG.
This problem also occurred between 2000 and 2005, and a large area was required to construct the memory cell array.

(Object of the Invention) An object of the present invention is to solve such problems and to provide a memory circuit in which the area of the memory cell is reduced by arranging a MOS transistor at the intersection of the address line and the memory cell output line. It is about providing.

(Structure of the Invention) The structure of the present invention is such that in a memory circuit in which each static memory cell constituted by 0MO8 transistors has he pairs of address lines and word lines for selecting this memory cell, the number of address lines By introducing a transistor string in which P-type or N-type MOS transistors each having a gate' [4L pole and connected in series between one memory cell output and the plurality of word lines, the transistor string The P-type M(J
The present invention is characterized in that the pair of address line and word line can be selected by a combination of an ST7 transistor and an N-type MOS transistor.

Conventional memory circuits use metal wiring at intersections to avoid intersections between memory cell output lines and address lines, which has limitations on mask patterns. At the intersection ~ 108 to 7
This method avoids the conventional constraints and reduces the area occupied by the memory cell by forming a transistor and making the transistor a P-type MO8 transistor or an N1MU3 transistor.

(Example) Hereinafter, the present invention will be explained in detail with reference to all the drawings.

FIG. 3 is a circuit diagram of a memory cell having two address lines and two word lines according to an embodiment of the present invention, and FIG. 4 is a mask pattern configuration diagram when the mask pattern of FIG. 3 is designed. . In the third section, P-type Mus transistors Q9 to Q12 are added by δ compared to FIG. Operation of this circuit (l-explain.

Address HA1+ A2! The words IfMWx, W1 and W2 . P-type MO8 with M W2)
Ransistor Q3. When the address line A1 is selected (active at H level), the NgMO8 transistor Ch and Q2 are conductive.
is not selected, so it is at Low level, and P
The type MO8) transistor Q9°Qll is conductive and electrically connected to the input/output word HW 11 Wl. At this time Q
IO, Ql2 is a P-type transistor, non-conducting - Q2
, since Q7 is an N-type transistor, it is non-conducting and the memory cell is.

Input/output word? fM W21 Not electrically connected to W2〇On the other hand, if address iAz is selected, Q1o+Q2
, Q7, Ql2 are conductive, Ql, Q9+Q11
Since 1Q8 is not conductive, the memory cell is electrically connected to the human output take line W2°, and the input/output data output wt,
With wt (we don't connect emotionally. Also, address Iwao Al.

When A2 is not selected (Low level) % input/output cuff 1 HW 1 , transistor Q for W I K
Since t+Qs is non-conductive, the memory cell is not electrically connected and the input/output turns iW2. For W2, transistor Q2. Since Q7 is non-conductive, it is not electrically connected to the Kutumori cell.

In this way, when the output of a memory cell is electrically connected to the input/output word output through a transistor selected by one address line.

P is placed at the intersection of other address lines and the output of the memory cell.
By arranging a type MOS transistor, the same result as when wiring is changed to gold maple wiring can be obtained.

(Effects of the Invention) According to the present invention, the conventional structure is changed to gold maple wiring, and in order to conduct wiring, 98 contacts per unit cell and 4 gold maple wiring areas are required. On the other hand, M(J8
) Since the transistor is configured only as an iP type MOS transistor, the area occupied by the memory circuit can be reduced.

(Other Embodiments) In this actual MM example, a circuit with two address lines, two word names, and a memory cell that covers all sides has been described, but with a similar configuration, multiple (n) address edges and As for the memory cell circuit having a word line, as shown in the circuit diagram in FIG. It's important to make it smaller.

1. In the explanation of this embodiment, the purchase of the address line "
1" is selected, the memory cell selection transistor is N-type MO8? However, as shown in the circuit diagram in Figure 6, when the logic "0" of the address line is in the selected state, the memory cell selection transistor/storage is made into a P-type MO8 transistor. It is possible to construct a similar circuit in Tami

[Brief explanation of the drawing]

1 and 2 are configuration diagrams of two conventional address lines and their mask patterns, FIGS. 3 and 4 are circuit diagrams of an embodiment of the present invention and their mask turn structure diagrams, and FIG. 5 , and FIG. 6 are circuit diagrams of second and third embodiments of the present invention. In the diagram, 10...Kanagi wins, 11...
... Polysilicon wiring, 12... Diffusion layer wiring,
13...Contact, A1+A2...An・
...Memory cell selection address lines, Wl, W2...
・Wn...Memory cell positive phase word? fM-Wl
l W2...weak. ...Memory cell reverse phase word line, Vcc...Short source line, GND...
Ground wire, Ql + Q2 + Q4 + Q6~Q9・
...N type MO8) transistor, Q3+Qs+Qe
~Q12...Pff1MO8) Transistor 0 Foil 7 Figure 84 Figure

Claims (1)

[Claims] C & 10] In a memory circuit in which each static memory cell configured with a plurality of transistors has a plurality of M address lines and word line bears for selecting this memory cell, each of the address lines of the previous ga & i is connected to a gate electrode. By connecting a transistor string in which P-type or N-type MOS transistors connected in series are connected between the output of the memory cell in the 11th direction and the word line l\iI&number, A memory circuit in which the address line and word line bare can be selected by a combination of a P-type MOS transistor and an N-type MOS transistor.