JPS60187057A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enable to perform an etching for formation of a collector electrode with sufficient controllability by a method wherein an AlGaAs layer is provided between a GaAs contact layer and a GaAs collector layer. CONSTITUTION:A non-doped GaAs buffer layer 22, an n<+> type GaAs contact layer 23, and n<+> type AlGaAs layer 24, an n type GaAs collector layer 25, a p type GaAs base layer 26, an n type AlGaAs emitter layer 27, and a GaAs contact layer 28 are formed on a semiinsulative GaAs substrate 21 successively. Then, a p<+> type base contact region 29 is formed. Subsequently, a mask 30 to be used to cover the layers 27 and 28 is provided, and when a dry etching is performed, the layers 25 and 26 are etched, and the etching is brought to come to a stop on the layer 24. Then, the exposed layer 24 is removed. According to this constitution, the layer 24 is used as an etching stopping layer, and the depth of etching can be controlled accurately, thereby enabling to prevent the increase in resistance value of the lead-out part of a collector electrode 32.

Description

[Detailed Description of the Invention] (a) Technical Field of the Invention The present invention enables deep selective etching to form a semiconductor device, particularly a collector electrode lead-out portion, to be performed with good controllability, and can be manufactured with good reproducibility. This paper relates to the structure of a heterojunction bipolar transistor.

(b) Background of the technology Microelectronics has become the foundation of modern industrial progress and has a major impact on social life. Currently, the mainstay of microelectronics is silicon (St) semiconductor devices ranging from transistors to ultra-large scale integrated circuit devices, and miniaturization of transistor elements has been promoted to improve characteristics and increase the degree of integration.

Furthermore, in order to improve operating speed beyond the limits based on the physical properties of silicon and reduce power consumption, we developed gallium arsenide (Ga), which has a much higher carrier mobility than silicon.
Semiconductor devices using compound semiconductors such as Ag) have been developed.

Among transistors using compound semiconductors, field-effect transistors are being developed first due to their simple manufacturing process, but as the manufacturing process for compound semiconductor devices progresses, bipolar transistors are also being developed. ing. In compound semiconductor bipolar transistors, molecular beam epitaxial growth (hereinafter referred to as MBE) or metal organic pyrolysis vapor phase epitaxy (hereinafter referred to as MOC) is used as an epitaxial growth method for compound semiconductors.
The heterojunction bipolar transistor, which has become possible with the development of the VD method (abbreviated as the VD method), is particularly promising.

That is, when compared with the same element area, a bipolar transistor has a larger current driving ability than a field effect transistor, and in particular, a heterojunction bipolar transistor in which a heterojunction is provided between an emitter and a base has the highest current driving ability. Furthermore, since the current direction of the main portion that determines the operating speed is perpendicular to the semiconductor layer, it is much easier to reduce the size of a field effect transistor, whose size is set by a lithography method.

(c) Prior Art and Problems A conventional example of a heterojunction bipolar transistor is shown in FIG.

In the figure, 1 is a semi-insulating GaAa substrate, 2 is a non-doped GaAs buffer layer, 3 is an n+ type GaAs contact layer, 5 is an n-ya GaAg collector layer, and 6 is a p-type G
aAs base layer, 7 is nR aluminum ξ gallium arsenide (
8 is an n+full GaAs contact layer, and 9 is a p+ type base contact region.

10 is a collector electrode, 11 is a base electrode, and 12 is an emitter electrode.

In a heterojunction bipolar transistor, at least the emitter region is made of a semiconductor having a larger forbidden band width than the base region.

In the above example, the base layer 6 is made of p+ type GaAs, and the emitter layer 8 is made of n-type AtGaA, which has a larger forbidden band width.
It is composed of s. Due to this difference in forbidden band width,
This improves the ratio of the current caused by electrons injected from the emitter to the base to the current caused by holes injected from the base to the emitter, that is, the current injection efficiency, and at the same time expands the degree of freedom in selecting the impurity concentration of the base region, etc. There is. .

In the conventional example shown in FIG. 1, an emitter electrode 12. The base electrode 11 and collector electrode 10 are taken out by JCL (Eknitter Co.
This is to obtain high-speed operation without delay due to accumulation time by using the UPLED Logic circuit. In order to provide these electrodes, selective etching to form the p+ type base contact region 7 and introduction of acceptor impurities and selective etching to expose the n+ type GaAs contact layer 3 are required.

In particular, in the selective etching to expose the n''mGa, As contact layer 3 where the collector electrode lO is provided, nm
It is necessary to etch the GaAa contact layer 9, the nff1AtGaAs emitter layer 8, the p+ type GaAl base contact region 7, and the n-type GaAs collector layer 5, but the etching is finished leaving a sufficient amount of the n+ type GaAl5 layer 3. It is extremely difficult to control this because the etching depth is large, and the resistance value tends to increase due to residual n-type GaAs collector layer 5 or excessive etching of n+-type GaAs contact layer 3.

(d) Purpose of the Invention The present invention solves the above-mentioned problems with respect to AtGaAs/GaAs heterojunction bipolar transistors, and makes it possible to perform etching for forming a collector pole with sufficient controllability. The purpose is to provide structure.

(e) Structure of the Invention The object of the present invention is to provide a first
a gallium arsenide contact layer of a conductivity type, and a gallium arsenide collector layer of a first conductivity type and a gallium arsenide collector layer of a second conductivity type are formed on the gallium arsenide contact layer via an aluminum gallium arsenide layer of a first conductivity type. a gallium arsenide base layer;
This is achieved by a semiconductor device in which an aluminum gallium arsenide emitter layer of a first conductivity type is provided, and a collector electrode is provided in contact with the gallium arsenide contact layer.

(f) Embodiments of the Invention The present invention will be described below with reference to the drawings and its manufacturing method by way of embodiments.

FIGS. 2(a) to 2(e) are step-by-step sectional views showing an embodiment of the present invention.

Refer to FIG. 2(a), a semi-insulating GaAa substrate 21 is coated with MOCVD or MBE.
The following semiconductor layers are sequentially epitaxially grown using a method. However, in the table below, composition ratio X of 0 means GaAs, 0
．． 3 indicates Ato, 3 Gio, 7As, each number is 1
Give an example.

Sign Composition ratio Impurity concentration Thickness
lXl0" 50 25 0 n-lXl0" 300 24 0.3 n-2X 10" 1~223 0 n
-2X10'' 200 22 0 Non-doped 300 In other words, in the structure according to the present invention, compared to the conventional example, n+ type), Lo, a Ga Q, ?A11
The layer 24 is a modified GaAs contact layer 23 and an n-type GaA layer.
s collector layer 25, and its thickness is made as thin as, for example, 1 to 2 (nm).

Referring to FIG. 2(b), an emitter region is formed. In this embodiment, the n+ type GaAs layer 28 and nff1Ato, aGao, 7As
Selective etching to remove the layer 27 other than the emitter region is performed using, for example, a mixed solution of hydrofluoric acid (HF), hydrogen peroxide (HtO), and water (HlO).

Next, for example, beryllium (Be) is given an energy of 30
(Key) to a dose of about I x 10''CM), for example, infrared flood.

This is activated by an annealing method to form a p+ type base contact region 29.

Refer to FIG. 2(e) A mask 30 covering the emitter region and base contact region is provided, and etching is performed by a dry etching method such as a reactive ion etching method using carbon dichloride difluoride (CC4FJ) as an etchant.
According to the dry etching method using CL and F as etchants, GaAs is etched, but A9aAs is not etched, and the p-type GaAs base layer 26 and the n-type GaAs collector layer 25 are etched.
, 3GaO, 7As layer 24, the etching stops.

Refer to FIG. 2(d). The n+ type ALO, aGaO, and 7As layers 24 are removed using the aforementioned HF HtO*H20 etching solution. :nm]/
The n-type Azo, aGBO, and 7AB layers 24 can be removed by etching for about 1 to several seconds. The n+ type GaAs contact (7tj523), which is much thicker than this layer, does not actually change in thickness by this short-time etching.

Referring to FIG. 2(s), a groove 31 sufficiently reaching the non-doped GaAs layer 22 is provided for element isolation. Next, for example, gold/germanium/
Nirektaeg using gold (AuGe/Au).../? 32 electrodes ♂ 1 electrode A4 are arranged, for example, gold/zinc/gold (
A base electrode 33 is provided using Au/Zn/Au).

As is clear from the manufacturing method of the embodiment described above, AtG between the collector layer and the collector contact layer according to the present invention
aAsJ- is GaA@ with this as an etching stop layer.
The selective etching enables accurate control of the etching depth and prevents an increase in the resistance value of the collector electrode lead-out portion.

Although the above embodiment is an n-p-n junction, a p-n-p junction in which the collector and emitter are p-type and the paste is n-type is used.
The present invention can be similarly applied to heterojunction bipolar transistors.

(g) As described in the detailed description of the invention (by the structure of the present invention, the collector electrode lead structure, which requires deep selective etching of a petrojunction bipolar transistor, can be accurately formed with good controllability, and this can be used as a device). It becomes possible to stably provide semiconductor devices such as integrated circuit devices with good reproducibility.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing a conventional example of a heterojunction bipolar transistor, and FIGS. 2(a) to 2(e) are step-by-step sectional views showing an embodiment of the present invention. In the figure, 21 is a semi-insulating GaA1 substrate, 22 is a layer,
27 is an n-type AtGaAs emitter layer, 29 is a p+ type base contact region, 30 is a mask, 31 is a groove, 32 is a collector electrode, 33 is a base 11[, and a4 is an emitter electrode. Grass 11Δ Thing 2 Figure (4) Hayabusa 2 Figure 2A

Claims (1)

[Claims] a gallium arsenide contact layer of a first conductivity type on a gallium arsenide semiconductor substrate;
A semiconductor comprising: a gallium arsenide paste layer of a conductivity type; an aluminum gallium arsenide emitter layer of a first conductivity type; and a collector electrode provided in contact with the gallium arsenide contact layer. Device.