JP2522067B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a hetero structure.

(Prior Art) In recent years, research and development of a compound semiconductor device using a heterojunction material has been particularly active. Generally, in a method of manufacturing a compound semiconductor device including a heterojunction, a crystal dry etching technique having high selectivity, high uniformity and low damage is important. Conventionally, as a method of selectively etching GaAs in a semiconductor crystal composed of AlGaAs and GaAs, for example, as shown in “Technical Review of Japan”, Vol. 88, No. 354 (1989), page 23, CCl ₂ F ₂ There is a method using reactive ion etching with a reactive gas consisting of He and He.

(Problems to be Solved by the Invention) In a compound semiconductor, for example, the surface of a GaAs crystal is unstable, and a natural oxide film is formed on the crystal surface when the crystal surface comes into contact with the atmosphere. With the reactive gas used in the conventional manufacturing method, the etching rate of the natural oxide film is small,
The time until the natural oxide film is removed varies on the wafer surface, which is one of the major causes of deterioration of etching uniformity. Therefore, in order to improve the uniformity, the etching time is lengthened to reduce the variation. However, in this case, etching in the direction vertical to the substrate surface is high in controllability because etching is stopped in AlGaAs because the etching rate ratio between GaAs and AlGaAs is large, but etching in the horizontal direction relative to the substrate surface is GaAs. Since the crystal reacts with the chlorine reactant and etching progresses, side etching occurs and the problem of lack of control remains.

An object of the present invention is to solve the above problems, particularly to improve the controllability in the horizontal direction with respect to the substrate surface, suppress side etching, and manufacture a semiconductor device including a highly uniform and low damage dry etching process. To provide a method.

(Means for Solving the Problems) In the present invention, a first compound semiconductor layer containing at least one of Al and In is formed on a semiconductor substrate, and Al is also formed thereon.
Stacking a second compound semiconductor layer not containing In,
A step of performing plasma treatment using a mixed gas containing at least hydrogen gas and another element gas, and a halogen gas whose main constituent elements are at least one of chlorine and bromine and fluorine continuously after the plasma treatment. A step of selectively etching the second compound semiconductor layer by a reactive ion etching method using a reactive gas containing at least hydrogen, the hydrogen gas being higher than a partial pressure ratio of the other element gas. A method for manufacturing a characteristic semiconductor device.

(Operation) FIG. 3 shows the dependence of the etching rate of GaAs in the plasma treatment of the present invention on the partial pressure ratio of CCl ₂ F ₂ and H ₂ . Further, the plasma treatment of the present invention is performed for 10 minutes, and 500 Å G when continuously performing reactive ion etching using CCl ₂ F ₂ and He
FIG. 4 shows the progress of etching of aAs and of AlGaAs. The high frequency energy of etching is
0.1 W / cm ² , gas pressure is 5P in the case of plasma treatment
a, 10 Pa in the case of the reactive ion etching. According to the method of manufacturing a semiconductor device of the present invention, for example, before performing reactive ion etching of GaAs, plasma treatment using a mixed gas of CCl ₂ F ₂ and H ₂ is performed, so that the natural state existing on the GaAs surface is Since the oxide film is removed, the etching start time is shortened in the reactive ion etching using CCl ₂ F ₂ and He for etching the second semiconductor layer. Therefore, it is possible to reduce the delay of the etching start time that has conventionally occurred, and it is possible to perform desired etching in a short time. Further, in the present invention, since there is no variation in etching start time, uniform etching can be performed. Further, since the supply amount of the fluorine reactant for performing the selective etching is about the same as that in the conventional technique, the controllability is controlled not only in the direction vertical to the substrate surface but also in the horizontal direction to the substrate surface. Controllability is also improved. In particular, the etching controllability in the horizontal direction with respect to the substrate surface is improved, and it is possible to provide a fine processing technology with fine processing, high control, and low damage, and a highly reliable semiconductor device can be realized with high reproducibility and high yield.

(Embodiment 1) FIGS. 1 (a) to 1 (d) are cross-sectional views of the structure of a main part of each step of a semiconductor device for explaining an embodiment of a method for manufacturing a semiconductor device of the present invention. Is.

First, as shown in FIG. 1 (a), a semi-insulating GaAs substrate 1
The first GaAs layer 2 is 5000 Å, the N-type GaAs layer 3 doped with Si 2 × 10 ¹⁸ cm ^-3 is 100 Å, and the first AlGaAs layer 4 is 200 Å.
Å, 2nd N-type GaAs layer doped with Si 2 × 10 ¹⁸ cm ^-3
12 to 500Å continuously epitaxially grow. Next, as shown in FIG. 1B, a resist 13 is applied to open the gate region. Next, as shown in FIG. 1 (c), the second N-type GaAs layer 12 in the gate region of the field effect transistor is removed.
Plasma treatment is performed using a reactive gas of CCl ₂ F ₂ and H ₂ , and selective etching is continuously performed by a reactive ion etching method using a mixed gas of CCl ₂ F ₂ and He. In the plasma treatment, the partial pressure ratio of gas is H ₂ higher than that of CCl ₂ F ₂ , and the gas pressure is 5 Pa. In the etching by the reactive ion etching method, He is lower than CCl ₂ F ₂ and the gas pressure is 10 Pa. Next, as shown in FIG. 1D, Al is vapor-deposited and the gate electrode 8 is formed by the lift-off method to form a field effect transistor.

In this example, the standard deviation of the threshold voltage of the obtained device was as good as about 11 mV, and the damage due to the reactive ion etching was also extremely small. Similar results were obtained when the gas pressure for plasma treatment was in the range of 0.01 Pa to 10 Pa. In addition, a stacked semiconductor device having a two-dimensional electron gas layer high electron mobility transistor, a first semiconductor layer, an insulating layer and a second semiconductor layer can be similarly realized.

Second Embodiment Next, another embodiment of the present invention will be described with reference to the drawings.

2 (a) to 2 (e) are cross-sectional views of a main part structure of each step of the semiconductor integrated device, which are shown for explaining one embodiment of the method for manufacturing the semiconductor integrated device of the present invention.

First, as shown in FIG. 2 (a), a semi-insulating GaAs substrate 1
The first GaAs layer 2 is 5000 Å, the N-type GaAs layer 3 doped with Si 2 × 10 ¹⁸ cm ^-3 is 100 Å, and the first AlGaAs layer 4 is 200 Å.
Å, the second GaAs layer 5 is 50 Å, the second AlGaAs layer 6 is 50 Å,
The third GaAs layer 7 is continuously epitaxially grown to 200 Å. Next, as shown in FIG. 2 (b), the third GaAs layer 7 in a partial region is subjected to a plasma treatment using a reactive gas of CCl ₂ F ₂ and H ₂ to continuously perform CCl ₂ F. Selective etching is performed by the reactive ion etching method using a mixed gas of ₂ and He. In the plasma treatment, the gas partial pressure ratio is CC
high of H ₂ with respect to l ₂ F _2, the gas pressure is 5 Pa. The etching by the reactive ion etching method is CCl ₂
He is lower than F ₂ and the gas pressure is 10 Pa. Second
The gate electrode 8 is formed using WSi as shown in FIG. 2C, and Si is implanted at 150 KeV and 1 × 10 ¹⁴ cm ^-2 using the gate electrode 8 as a mask as shown in FIG. 2D. , Then 80
Heat treatment is performed at 0 ° C. to form a contact region 9, and then, as shown in FIG. 2 (e), an ohmic electrode 10 is formed on AuGe / Ni.
Are formed by using.

In this example, the standard deviation of the threshold voltage of the obtained device was as good as about 12 mV, and the damage due to the reactive ion etching was also extremely small. The gas pressure is 0.01
Similar results were obtained in the range of Pa to 10 Pa. Besides, a stacked semiconductor integrated device having a high electron mobility transistor having a two-dimensional electron gas layer, a first semiconductor layer, an insulating layer and a second semiconductor layer can be similarly realized.

(Effects of the Invention) As described above, the present invention can realize selective reactive ion etching of a compound semiconductor crystal capable of highly uniform, low damage and highly precise microfabrication. It has an effect that an excellent semiconductor device can be realized with high yield.

[Brief description of drawings]

1 (a) to 1 (d) are cross-sectional views showing the structure of a main part of each step of the semiconductor device shown for explaining one embodiment of the present invention. 2 (a) to 2 (e) are cross-sectional views showing the structure of a main part of each step of the semiconductor integrated device shown for explaining another embodiment of the present invention. FIG. 3 is a diagram showing the GaAs etching rate dependence of the mixing ratio of CCl ₂ F ₂ and H ₂ in the plasma treatment of the present invention. FIG. 4 is a diagram showing the time dependence of GaAs etching in the present invention. 1 ... Semi-insulating GaAs substrate, 2 ... First GaAs layer, 3 ...
First N-type GaAs layer, 4 ... First AlGaAs layer, 5 ... Second
GaAs layer, 6 ... second AlGaAs layer, 7 ... third GaAs
Layer, 8 ... Gate electrode, 9 ... Contact area, 10 ...
Ohmic electrode, 11 ... third AlGaAs layer, 12 ... second N-type GaAs layer, 13 ... resist

Claims (2)

(57) [Claims] 1. A first compound semiconductor layer containing at least one of Al and In is formed on a semiconductor substrate, and Al is also formed on the first compound semiconductor layer.
Stacking a second compound semiconductor layer not containing In,
A step of removing a natural oxide film on the surface of the second compound semiconductor layer by performing plasma treatment using a mixed gas containing at least hydrogen gas and another element gas; and continuously removing chlorine or bromine after the plasma treatment. A step of selectively etching the second compound semiconductor layer by a reactive ion etching method using a reactive gas containing a halogen gas containing at least one of them and fluorine as a main constituent element; The method for manufacturing a semiconductor device, wherein the gas is higher than the partial pressure ratio of the other elemental gas. 2. The first compound semiconductor layer is an AlGaAs layer,
2. The method for manufacturing a semiconductor device according to claim 1, wherein the second compound semiconductor layer is a GaAs layer.