JPS60186146A - Regenerating circuit for bit timing - Google Patents

Abstract

PURPOSE:To discriminate a base band signal in the best phase by supplying a regenerated bit timing signal to an identifier which identifies a base band obtained by demodulating a phase-modulated signal with a phase control signal from the identifier. CONSTITUTION:The bit timing BT of a base band signal applied to a terminal 40 is extracted by an extracting circuit 28 for the bit timing BT and applied to a phase locked part 29. The locked part 29 is controlled through a phase-locked loop so that a voltage-controlled oscillator 25 synchronizes with the BT signal, and the output of the oscillator 25 is applied to a phase control part 30. The phase control signal applied from the identifier to a terminal 41 is a digital signal which varies in the duty factor of pulses with a phase controlled variable and this is integrated by a voltage converter 31 to extract a DC component corresponding to the duty factor. The varactor diode 301 of the control part 30 is controlled with the DC signal and the phase of the signal from the oscillator 254 is rotated; and the signal is converted by a converter 27 into a digital signal, which is supplied from a terminal 42 to the identifier as the best reproduced BT signal for the identification of the base band.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a bin 1 timing recovery circuit, and more particularly to a bit timing recovery circuit used in a digital jji% line system using a multi-level orthogonal amplitude modulation method. be.

tb> Prior Art and Problems FIG. 1 shows a block connection diagram of a demodulator including a conventional bit timing recovery circuit.

In the figure, 1 and 3 are hybrid circuits, 2.4 are phase detectors, 5 and 7 are amplifiers, 6 is a carrier regeneration circuit, 8,
9 represents a low-pass filter, 10 represents a discriminator, 12 represents a bit timing recovery circuit, and 13 to 15 represent terminals.

The operation of the block connection diagram shown in FIG. 1 is as follows.

The received phase modulated wave is sent to terminal 13 and hybrid circuit 1.
and is applied to phase detectors 2 and 4.

Regenerated carrier waves having phases different by 90 degrees from the carrier wave regeneration circuit 6 are applied to the phase detectors 2 and 4 through the hybrid circuit 3, so that Hoenepando signals orthogonal to each other are demodulated. This baseband signal is applied to a discriminator 10 through an amplifier 5.7 and a low-pass filter 8, 9, respectively.

Here, (II) one of the Heashunt signals, for example, a part of the output of the amplifier 7 is applied to the bit timing regeneration circuit 12 to extract the reproduced bit timing 1'. This reproduced bit timing is supplied to the identification circuit 10. The above-mentioned Heath hand signal is identified and the original data is taken out to terminals 14 and 15.

FIG. 2 shows a more detailed block connection diagram of the bit timing regeneration circuit 12 in FIG. 24 is a phase converter/calibrator, 25' is a voltage controlled oscillator, 26 is a low-pass filter, 27 is a converter, 28 is a bit timing signal extractor, 29 is a phase Synchronization part, 40
and 42 respectively open the terminals.

The operation of the circuit shown in FIG. 2 is as follows.

Headphone 1 added to terminal 40: Signal to pitch I-
The timing signal extraction section 28 extracts the via +- timing signal and applies it to the phase synchronization section 29 . Therefore, the voltage controlled oscillator 2 whose phase is synchronized with the pinot timing signal
The output of 5, that is, the reproduction bit timing signal is output to the phase synchronization section 2.
It is taken out from 9. This signal is converted by the converter 27 into the reproduction hit timing of the digital f-digital signal, and is taken out from the terminal 42.

When identifying the demodulated Haes-Hand signal using timing, for example, in the case of multi-level quadrature amplitude modulation, it is difficult to identify Haes-Hand et al.'s signal at the optimal phase, resulting in fixed deterioration. There was a problem with .

The present invention, which has been overlooked in the problems of the prior art mentioned above, is to combine a bit timing self-generating circuit that can identify the Haeshand signal with the optimum phase into one. The purpose is 7.

? dl Structure of the Invention The purpose of the above invention is to demodulate mutually orthogonal Heashan 1 signals from phase modulated waves and demodulate the hint timing extracted from one of the Heashan 1 signals (using the self-generated hint timing synchronized with the f signal). In the demodulation section that identifies the hand signal with the discriminator, there is a voltage conversion section that extracts a DC voltage corresponding to the phase control signal obtained from the discriminator, and a voltage conversion section that is controlled by the output of the electric ratio conversion fls. a phase control unit that controls the phase of the self-growing Binotota Iminoji using a variable phase shifter;
This is achieved by providing a P1-timing regeneration circuit characterized in that the phase-controlled regenerated Pino-I timing from the phase control section is supplied to the discriminator. This is an example of a demodulator including a timing regeneration circuit.

In the figure, 1 and 3 are high 19F 1 circuits, 2 and 4 are phase detectors, 5.7 is an amplifier, 6 is a carrier wave regeneration circuit, 8,
9 is a low-pass filter, 16 is an 81 & separate device, 17 is a bit timing recovery circuit, 18 is an ISL adjustment circuit, 13 ~
15 indicates terminals, respectively.

The details of the operation of this demodulation section have already been described, so a brief explanation will be provided.

The phase modulated wave inputted from the terminal 13 is demodulated by the demodulation circuit 18 to obtain the Hessnot signals Id+ and G-ch, which are orthogonal to each other. Therefore, for example, the bit timing generation circuit 17 uses the Q-ch Heishan I'' (No. 8) to take out the tII raw bit timing to the terminal 42, but in the present invention, 1i11 using a phase control signal to control automatic death penalty
The phase of the timing is controlled so that the reproduction timing having the optimum timing can be obtained.

FIG. 4 is a diagram showing an example of the bit timing regeneration circuit of the present invention.

In the figure, 20 is an amplifier, 2122 is a tie auto, 23
is a bandpass filter, 24 is a phase comparator, 25 is a voltage controlled oscillator, 26 is a low-pass filter, 27 is a converter, 28
29 is the bit timing extraction section, 29 is the phase synchronization section, and 3 is the bit timing extraction section.
0 represents a phase control section, 302 represents a resistor, 301 represents a variable capacitance diode, 31 represents a voltage converter, and 40 to 42 represent terminals.

FIG. 4 is a more detailed block diagram of the bit timing recovery circuit 17 of FIG. 3, and its operation is as follows.

The bit timing extractor 2B extracts a bit timing signal from the hesnot signal applied to the terminal 40 and applies it to the phase synchronizer 29 as described above. Here, the output wave of the voltage controlled oscillator 25 is controlled by a phase locked loop a so as to be synchronized with the applied bit timing signal component.

The synchronized output wave of the oscillator 25 is applied to a phase control section 30.

On the other hand, the phase control signal included in the discriminator 16 for controlling the death penalty is taken out and applied to the terminal 41.

This control signal is a digital signal whose pulse duty factor changes depending on the phase control amount, and is integrated by an integrator comprised of, for example, a resistor and a capacitor, included in the voltage converter 31, to obtain a DC component corresponding to the duty factor. Take out.

With this DC voltage, the resistor 302 included in the phase control unit 30
The amount of phase rotation is changed by changing the capacitance of, for example, the variable capacitance diode 301 of a variable phase shifter configured with a variable capacitance diode.

Therefore, the reproduced bit timing signal from the voltage controlled oscillator 25, which has undergone phase rotation so as to be optimal for identification of the demodulated Haasband signal, is converted into a digital signal by the converter 27, and the reproduced bit timing signal is sent from the terminal 42 to the discriminator 16. supplied to

(l) As described in detail, according to the present invention, baseband signals are identified using reproduced focus timing that is phase-shifted in accordance with the phase control amount included in the phase control signal from the discriminator. By doing so, it was possible to always perform optimal identification and reduce fixed deterioration.

[Brief explanation of the drawing]

FIG. 1 is a block connection diagram of a conventional example of a demodulation section, FIG. 2 is an example of a conventional bit timing recovery circuit, FIG. 3 is a block connection diagram of a demodulation section using the present invention, and FIG. 4 is a block connection diagram of a demodulation section using the present invention. An example of the bit timing recovery circuit of the present invention is shown. In the figure, 20 is an amplifier, 2L 22 is a diode, 2
3 is a band filter, 24 is a phase comparator, 25 is a voltage controlled oscillator, 26 is a low pass filter, 27 is a converter, 2
8 is a bit timing extraction section, 29 is a phase synchronization section,
30 is a phase control section, 31 is a voltage conversion section, 40 to 42
indicate the respective terminals. 1st Cabinet 4υ 2nd item 3 Figure 11 ″

Claims (1)

[Claims] The mutually orthogonal base hand signals are demodulated from the phase shifter 11 waves, and a discriminator uses the stop bit timing synchronized with the bit timing signal extracted from one of the base pans 1-(8). Demodulation g to identify band signals
In lH, a voltage converter extracts a DC voltage corresponding to the phase control signal obtained from the discriminator, and a phase control unit that controls the phase of the reproduced bit timing by a variable phase shifter controlled by the output of the voltage converter. 7. A timing residing circuit comprising: a control section; and a phase-controlled reproduction bit timing from the phase control section is supplied to the discriminator.