JPS60185296A - Non-volatile randum access memory device - Google Patents

Abstract

PURPOSE:To increase the layout freedom of a memory cell and to reduce its occuplied area by using only one node output of an FF of a non-volatile memory cell by utilizing the fact that signal inversion forms the other information. CONSTITUTION:A non-volatile RAM is formed by a non-volatile memory cell 1 and a non-volatile memory cell 3 and the output of one node N1 of the FF forming the cell 1 is supplied to the cell 3. The 3rd TRT11 of the cell 3 is turned on when the output of the node N1 is at high level and the stored information is ''1'', and when the stored information is ''0'' and the output is inverted, turned off. Information is transferred from the cell 1 to the 3rd capacitor TC11 of a floating gate circuit element through the 4th TRT12, the 1st and 2nd capacitors C12, C13 and the 5th TRT15, a capacitor C15, etc. of the cell 3. The transfer of the information in the cell 3 to the cell 1 is executed similarly, so that the layout freedom of the memory cells is increased and the occupied area is reduced by using only one output of the node of the FF.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to non-volatile random access memory devices;
In particular, the present invention relates to a nonvolatile random access memory device configured by combining a volatile memory cell with a nonvolatile memory cell section using a floating gate circuit element.

Background of the Technology Recently, in state-of-the-art non-access memory devices, non-volatile memory cells have been created by combining volatile memory cells with floating date circuit elements, and non-volatile memory devices using such non-volatile memory cells have been developed. is being configured. In such static random access memory devices, the circuit configuration of each memory cell tends to be complicated and the size of each memory cell tends to increase. Since this tendency leads to a decrease in the reliability and degree of integration of memory devices, it is desired to improve this by devising a circuit configuration.

Prior Art and Problems FIG. 1 shows a memory cell used in a conventional non-volatile static random access memory device. This memory cell is volatile static memory cell part 1
and a nonvolatile memory cell section 2.

The volatile static memory cell section 1 has a seven-lip-flop configuration similar to that used in a typical volatile static random access memory device. Data is written and read in the volatile static memory cell section 1 via the agate transistor of the transformer 7 connected to nodes N and N2.

The non-volatile memory cell section 2 is an MIS (metal-insulator)
metal) transistors T5, T6 and T7, capacitor module CM1, capacitors C1, C2 and C3,
and a tunnel capacitor TC1 as a floating gate circuit element. Capacitor module C
M has a capacitance between the electrode and the other electrodes 1D2 and D3. The capacitance between the electrodes of the canopy module CM1 and the capacitance of the capacitor C3 are selected to be sufficiently larger than the capacitance of the tunnel capacitor TC1.

A capacitor that produces a tunnel effect when a voltage is applied between its electrodes is called a tunnel capacitor.

In the circuit shown in FIG. 1, the operation of transferring data from the volatile static memory cell section 1 to the nonvolatile memory cell section 2 will be described. For example, assume that node N1 is at a low level and node N2 is at a high level. In this state, the power
Raise HH from 0■ to 20 to 30V. At this time, since the node N1 is at a low level, the transistor T7 is in a cutoff state, and since the node N2 is at a high level, the transistor T5 is in an on state. Therefore, the potential of node N4 is at a low level (approximately 11 equal to VS2), and the power supply VHH is connected to the capacitor module.
Capacitance between electrodes D1 and D2 of CM1.

It is applied to a series circuit of the capacitance between capacitance and capacitor D3 and the capacitance of tunnel capacitor TC1. As mentioned above, the capacitance of the capacitor module CM1 is the tunnel capacitor TC,
Since the capacitance of VHH is sufficiently larger than that of VHH, most of the voltage of power supply VHH is applied to tunnel capacitor TC4. Therefore, electrons are injected from the node N4 to the node FG1 due to the tunnel effect, and the floating gate circuit of the transistor T6 is charged with negative charge, and the transistor T6 is turned off. Saving of data to the cell section 2 is completed.

On the other hand, when the node N1 of the volatile static memory cell portion l is at a high level and the node N2 is at a low level,
Transistor T7 is turned on and transistor T5 is turned off. Therefore, the electrode D of the capacitor C3, tunnel capacitor TC4 and capacitor module CM is
A power supply 'vI (□) is applied to the series circuit of capacitors between 5 and Dl, and most of the voltage of the power supply VHH is applied to the tunnel capacitor TO1 due to the capacitance relationship of each capacitor.In this case, the node N4 side is connected to the node Since the voltage is high on the N4 side, electrons from the synode FG (70-Ting gate circuit of transistor T6) are transferred to the node N4 due to the tunnel effect.
removed to the side. Therefore, the floating gate circuit, that is, the node FG1 is charged with positive charge, the transistor T6 is turned on, and the evacuation from the volatile static memory cell section 1 to the nonvolatile memory cell section 2 is completed.

Next, an explanation will be given of the operation when data in the nonvolatile memory cell section 2 is transferred to the volatile static memory cell section 1. First, power supply V. 0 and vHH are both OV, then the power supply V. Increase only 0 to 5v. If node FG,
If the node N2 is charged with a negative charge, the transistor T6 cuts off the connection between the node N2 and the capacitor C2. On the other hand, since the capacitor C1 is connected to the node N, the power supply V is applied. 0, the 7 lip-flop circuit is set to a low level on the node N1 side, which has a large load capacity, and a high level on the node N2 side.

Conversely, if electrons are extracted from the floating gate of transistor T6 and it is charged with positive charge, transistor T6 is turned on and node N2 and capacitor C2 are connected. Since the capacitance of capacitor C2 is selected to be larger than that of capacitor C4,
Power supply V. By raising 0, node N2 becomes low level,
The flip-flop circuit of the volatile static memory cell section 1 is set so that the node N1 becomes high level.

The above-mentioned nonvolatile static random access memory device is described in the specification of Japanese Patent Application No. 191039/1983.

However, in the memory cell of FIG. 1 described above, two cross-connected connection points of the seven lip-flops of the static memory, ie, node N.

and node N2 must be supplied to the non-volatile memory cell section, which reduces the degree of freedom in layout when memory cells are arranged in an integrated circuit, resulting in the There was a problem that the area occupied by the substrate became large.

OBJECTS OF THE INVENTION In view of the above-mentioned problems in the memory cells of conventional devices, it is an object of the present invention to convert information from an inverted signal at one node of a 7-lip flop in a volatile static memory cell section to a 7-channel node on the other side. Based on the idea of obtaining information on one node of the volatile static memory cell, when arranging the other memory cells on an integrated circuit, the degree of freedom in the layout is increased, and each memory cell The objective is to reduce the area occupied by the substrate.

Structure of the Invention In the present invention, one memory cell is configured by pairing a volatile memory cell section and a nonvolatile memory cell section for saving information stored in the volatile memory cell section,
The volatile memory cell portion includes first . the nonvolatile memory cell section includes a third transistor whose gate is connected to the gate of the second transistor;
a transistor, a fourth transistor that is turned on and off according to whether the third transistor is turned on or off, and a fourth transistor that is turned on or off according to whether the third transistor is turned on or off;
The first transistor has one electrode connected to each of the transistors.
．． a second capacitor, connected between the gate of the fourth transistor and the other electrode of the first capacitor;
and a third capacitor that causes a tunnel effect between electrodes, a fourth capacitor whose one electrode is connected to the gate of the fourth transistor, the first capacitor, and the third capacitor.
a fifth transistor whose gate is connected to a connection point with the capacitor of the second transistor and whose gate is in a floating state; By applying a write voltage to the other electrode of the fourth capacitor, the storage information of the volatile memory cell section is written to the nonvolatile memory cell section, and the fifth
A nonvolatile random access memory device characterized in that information stored in the nonvolatile memory cell section is recalled to the nonvolatile memory cell section by applying a signal from the second transistor to the gate of the second transistor. provided.

Embodiment of the Invention A circuit diagram of a memory cell used in a nonvolatile random access memory device as a first embodiment of the invention is shown in FIG. This memory cell comprises a volatile static memory cell section 1 and a non-volatile memory cell section 3.

The volatile static memory cell section 1 is similar to a conventional static memory cell including a flip-flop circuit, so a description thereof will be omitted. This flip-flop circuit has two cross-connected connection points: a first node N connected to the drain of the first transistor T, and a second node N2 connected to the drain of the second transistor T2. One pit of data is accumulated depending on whether the level is high or low. When one of the nodes N and N2 is at a high level, the other is at a low level.

The nonvolatile memory cell section 3 includes a third transistor T14.
, fourth transistor T12, first capacitor C12
, second capacitor C13, third capacitor TC11 as a floating gate circuit element, fourth capacitor C14, fifth transistor T13, capacitor C
and a capacitor C45.

4. The electrode on the other side of the capacitor C42 and the capacitor c1s is common to both. Capacitor C11, C4
The capacitances of both tunnel capacitors TC and C43 are selected to be sufficiently large compared to the capacitances of the third capacitors, ie, tunnel capacitors TC and 1. The capacitance of capacitor C45 is selected to be larger than the capacitance of capacitor C14.

The node N1 of the seven lip-flops of the volatile static memory cell section 1 is connected to the transistor T4. and the drain of transistor T15. The source of the transistor T13 is connected to the power supply ■s via the capacitor C45.
s (usually connected to OV at ground). Node N2 of volatile static memory cell section 1 is connected to power supply SS via capacitor C14. One electrode of the capacitor C1 is connected to the power supply Vss via the transistor T11, and is also connected to one electrode of the tunnel capacitor TC41 and the gate of the transistor T12.

A voltage from high voltage power supply VHH is supplied to the other electrode of capacitor C11 and the inner electrode of capacitor C43.

One common electrode of capacitors C42 and C43 is connected to the power supply "ss" via transistor T12. The other electrode of tunnel capacitor TC41 is connected to the other electrode of capacitor C42 and the gate of transistor T5. be done.

The operation of the aforementioned memory cell will be explained. Transfer of data in the volatile memory cell section 1 to the nonvolatile memory cell section 3 is performed as follows. When the node N of the 7 lip-flop of volatile static memory cell 1 is at a high level,
Transistor T11 is not in the on state, so one electrode of capacitor C11, tunnel capacitor TC1,
and the gate of transistor T+2 are connected to one electrode of transistor T1. (this connection point is referred to as node N4.), the voltage is at a low level approximately equal to the voltage of the power supply VSS. For this, the transistor T
, 2 are in the off state. At this time, when the power supply VHH is increased from O to about 20V, the voltage of about 20V will be applied to the capacitor C.
13, C12 and the tunnel capacitor TC41. Due to the magnitude relationship of the capacitances of the capacitors connected in series, the voltage of about 20V is mostly applied to the tunnel capacitor TC.

is applied between both electrodes. Tunnel capacitor TC11
When a voltage of about 20 V is applied between both electrodes of the tunnel capacitor, a voltage of about 10
Unless an electric field of MV/cm or more is applied, a tunnel effect occurs, and electrons flow from the node N,1 side to the gate circuit of transistor T13 (node FG, 1).
injected into. That is, it is charged with a negative charge. This state is maintained for a long time even if the power is turned off.

When node N, is at a low level, transistor T,.

is in the OFF state, and the node N,1 is in the 70-Ting state. When the power supply vHH is increased from 0 to approximately 20V, the capacitive coupling of the capacitor C11 causes the node N1 to
The voltage of 1 is approximately 20V. Therefore transistor T,2
is turned on, and the drain of the transistor T12 and one electrode of the capacitors C42 and C13 connected thereto have a voltage of approximately OV. As a result, approximately 20V
The voltage of capacitor C11, tunnel capacitor TC1
4, and a series circuit of capacitor C12. Due to the relationship between the capacitance sizes between these capacitors, most of the voltage of approximately 20V is applied between both electrodes of the tunnel capacitor TC11, and the tunnel effect causes the voltage to be applied from the node FG, 1 side to the node N1. Electrons are injected to the ° side, and nodes FG, , are charged with positive charges. This state is maintained for a long time even if the power is turned off. If nodes FG, . If T is charged with a negative charge, the transistor T, 3 is turned off.

Data accumulated in the nonvolatile memory cell section 3 (node F
(determined by the charging state of G11) to the volatile static memory cell unit 1 is performed as follows. When the power supply VCo of the flip-flop is increased from O to 5V, the node FG,.

If the transistor T13 is charged with a positive charge, the transistor T13 is on, and since the capacitor C15 is connected to the node N, the node N1 side of the flip-flop is set to a low level. That is, since the capacitance of capacitor C55 is set to be larger than that of capacitor C14, the load capacitance on the node N1 side is large and is set to a low level. If node FG,1 is charged with a negative charge, transistor T,3 is off and capacitor C15 is disconnected from node N, so the node N1 side of the flip-flop is set to a high level. Ru.

In other words, the node N2 to which the capacitor C14 is connected
Since the load capacitance is larger, it is set to a low level, and therefore the node N, is set to a high level.

A circuit diagram of a memory cell used in a nonvolatile random access memory device according to a second embodiment of the present invention is shown in FIG. This embodiment includes a volatile static memory cell section 1 and a nonvolatile memory cell section 4. The volatile static memory cell section 1 is similar to the first embodiment. The nonvolatile memory cell section 4 differs from the first embodiment in that a transistor T14 is provided on the node N1 side of the transistors T and 3 instead of the capacitor C15.

Array recall signal A is applied to the gate of transistor Ti4.
R is supplied. The array recall signal is applied to the power supply V when data is transferred from the nonvolatile memory cell section 4 to the volatile static memory cell section 1. A high level is supplied for a short time corresponding to the timing when 0 rises from 0 to 5■.

The operation of the second embodiment will be explained. The operation of transferring data from the volatile static memory cell section 1 to the non-volatile memory cell section 4 is the same as that in the first embodiment, and will therefore be omitted. Also, regarding the reference numerals of each element of the memory cell, the same reference numerals are used for the same elements as in FIG.

Data is transferred from the nonvolatile memory cell section 4 to the volatile static memory cell section 1 as follows. When the node FG11 is charged with positive charge, the transistor T13 is on, and the power supply V is applied. When 0 rises from 0 to 5■, if the signal AR is made high for a short time, the transistor T14 is turned on, and the node N1 is turned on.
is brought to the level of the power supply VsS for a short time, setting the node N1 of the flip 70 amplifier to a low level. When node FG11 is charged with a negative charge, transistor T,3 is in an off state, and node N, is disconnected from the power supply vsS, υ, regardless of the state of transistor T14, while node N2 is connected to a capacitor. Since C14 is connected, power supply ■. When 0 rises from 0 to 5v, node N2 is set to a low level, ie, node N is set to a high level. According to this embodiment, data in the nonvolatile memory cell section can be transferred to the volatile memory cell section without using the capacitor C15, and the area occupied by the memory cell can be reduced. Also, when the transistor T14 is cut off, the transistor T,
Since the drain voltage of 3 is at a low level, there is no possibility of hot electrons jumping from the drain to the gate, and fluctuations in the amount of charge in the floating gate circuit are prevented, making it possible to stably hold data for a long time. Become.

Effects of the Invention According to the present invention, a memory cell can be configured using information from only one of the cross-connected nodes of a volatile static memory cell. The degree of freedom in layout can be increased, and the area occupied by each memory cell on the substrate can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a memory cell used in a conventional nonvolatile static random access memory device, and FIG. 2 is a circuit diagram of a memory cell used in a nonvolatile random access memory device as a first embodiment of the present invention. 3 and 3 are circuit diagrams of a memory cell used in a nonvolatile random access memory device according to a second embodiment of the present invention. Engineering: Volatile static memory cell section, 2.3.4
...Nonvolatile memory cell section, C1, C2, C3, C1
1, C12, C15, C14, C45... Capacitor, CM,... Capacitor module, Dl, D2, D5... Electrode, T1, T2, T3, T4, T5, T6, T7, 'r++
, T12, T13, T14...MIS) transistor,
TCl, TCl, ... tunnel capacitor. Patent applicant Fujitsu Ltd. Patent agent Akira Aomizu Patent attorney Kazuyuki Nishidate Patent attorney Yukio Uchida Akira Yamaguchi

Claims (1)

[Scope of Claims] One memory cell is constituted by a pair of a volatile memory cell section and a nonvolatile memory cell section for saving information stored in the volatile memory cell section, and the volatile memory The cell section includes first and second transistors that are cross-connected, and the nonvolatile memory cell section includes a third transistor whose gate is connected to the gate of the second transistor;
a fourth transistor that is turned on and off in accordance with the on and off states of the third transistor; first and second capacitors each having one electrode connected to the fourth transistor; and the fourth transistor. connected between the gate of 1 and the other electrode of the first capacitor,
and a third capacitor that causes a tunnel effect between electrodes, a fourth capacitor whose one electrode is connected to the gate of the fourth transistor, the first capacitor, and the third capacitor.
a fifth transistor whose gate is connected to a connection point with the capacitor of the second transistor and whose gate is in a floating state; By applying a write voltage to the other electrode of the fourth capacitor, the storage information of the volatile memory cell section is written to the nonvolatile memory cell section, and the fifth
A nonvolatile random access memory device, wherein information stored in the nonvolatile memory cell section is recalled to the volatile memory cell section by applying a signal from the second transistor to the gate of the second transistor.