JPS60183626A - Information processing unit - Google Patents

Abstract

PURPOSE:To obtain a data processing unit with less occupied area without decreasing the CPU processing capability by selecting the conventional software interruption processing and an adaptor for automatic transfer processing when an A/D conversion end signal is generated. CONSTITUTION:When an I/O request attended with the A/D conversion end in an A/D converter 400 is generated, a CPU510 stops the program processing under execution and the CPU510 itself transfers data automatically while holding various states and data at their locations. When the automatic data transfer is finished, the CPU510 executes again the execution of the stored program without using overhead. Thus, the software sees no intermission of the program, as if the automatic data transfer processing of the A/D conversion data were inserted automatically during the program processing. Thus, the frequency of generation of A/D conversion interruption attended with the software is minimized and the load of the CPU is relieved for the share.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing device incorporating an A/D converter.

In recent years, LSI technology has made remarkable progress, and digital processing technology is progressing like a torrent compared to analog processing technology. Under these circumstances, the A/D converter is a measurement controller, measuring instrument 1 communication 1 image processing.

It is needed when combining analog signal processing fields such as audio processing, television, and audio with digital technology, especially light sensitivity, heat (temperature), pressure, and sound.

It is essential as a technology for converting analog quantities such as flow rate into digital cans, and is expected to have high performance.

On the other hand, progress in LSI technology has led to central processing units (hereinafter referred to as %CP)
A normal microcomputer includes a memory, a general-purpose input/output board (U), a clock generation circuit, and a timer/counter function.

It incorporates an A/D converter as well as DMA, serial interface, etc., and mounts these on the same semiconductor substrate, resulting in high concentration.

An example of analog data processing of a conventional A/D converter in this background will be described below with full reference to the block diagram of FIG.

The A/D converter 100 has analog inputs 101-1 to 101-10.
1-8. Multiplexer 102% channel specification pin) 1
A/D channel mode register 103 with 03-1 and A/D conversion completion flag 103-2, sample and hold circuit 104, ladder resistor network 105, voltage comparator 10 (i, sequential comparison 1 /Jista (hereinafter referred to as
(referred to as SAR) 107° controller 108. and a conversion result register (hereinafter referred to as T, CRR) 109,
For example, an 8-bit A/D conversion value is obtained by successive approximation.

First, CPtJ is A/D channel mode register 1
Write the entire value to the channel designation bit 103-1 of 03.

At the same time, the A/D conversion completion flag 103-2 is reset. A/D channel mode register 103
The analog input signal 101-1i selected according to the designation is sambling in the sample hold circuit 104, and its output becomes one input of the voltage comparator 106. Based on the difference between the analog input and the voltage tap selected by the tap decoder of the ladder resistor 105, the voltage comparator 106U sets the corresponding digital data in the 5AR 109 from the upper bit. That is, one comparison in the voltage comparator 106 sets one bit of digital data, and by repeating this comparison operation, an 8-bit A/D conversion value is set in 5AR 109 for one analog human input 101-1. be done. The four young fruits are latched into CRR109, and
? A of IVcA/D channel mode register 103
/D conversion completion flag 103-2 is set. cP
U must always check the A/D conversion completion flag t03-2 while the SA/D converter 100 is converting data after receiving the A/D conversion execution command and wait for the A/D conversion completion flag to be set. No. When it is confirmed that the A/D conversion completion flag is set, the A/D change value h7'' held in cPUl-j and cRR 109 is read out and stored in the memory.

Such VCs and conventional microcomputers with built-in A/D converters must constantly monitor the completion of conversion during A/D conversion, and the main processing that the CPU should normally perform cannot be performed during that time, resulting in less efficient execution. was extremely bad.

Conversion value setting completion flag 1 as an improvement to the above drawbacks
There is a method of generating an interrupt to the CPU at the same time the converted value is stored in the CRR 109 without using 03-2. This method will be explained with reference to the block diagram of FIG. 2 and the flowchart of FIG. 3. The microcomputer 200 executes ff1s 201, program memo 1J202. Data memory 203, A/D converter 204. and an A2B interrupt control unit 206, each of which is interconnected via an internal data bus 205.

Execution unit 201rrJ, program counter (hereinafter referred to as P
C) 201-1. Program status word (
psw) 201-2 and a general-purpose register set 201-3', and executes the entire program based on the instruction code read from the program memory 202.
Processed data is stored in data memory 203. A/D converter 204 A/D converts 1 byte of CRR204-2' (with z, 7sl' input 204-1, CRR2
When the storage to 04-2 is completed, the conversion completion signal 210 is activated.

Then, the A2B interrupt control unit 206 is notified that the conversion has been completed. In response to this, the A2B interrupt control unit 206 activates the interrupt request line 211'ff and instructs the execution unit 201 to generate an A2B interrupt request)l'TI7. (The execution unit 201 executes the A2B interrupt processing.

Here, software processing 711 due to A2B interrupt
13' will be described using the flowchart in FIG. In this software processing, a conversion value storage area 203-1 is set in the data memory 203, and a conversion value ID storage area 203-1 is set in the data memory 203.
Address information specifying 03-1 and conversion number information ts
is the conversion parameter save area 20 in the data memory 203
It is preset to 3-2.

When notified of the completion of conversion, the execution unit 201 executes conversion interrupt processing. First, in order to preserve the processing Okaya in the trench, each content k -u'? It is then saved to another area prepared as the stack area 203-3. Next, the address is read from the conversion parameter save area 203-2 to the conversion value storage area 203-1 and loaded into the pointer. Thereafter, all converted values are extracted from the CRR 204-2 and stored in the converted value storage area 203-IK specified by the pointer. When the number of conversions reaches the predetermined number of times Vc, it is assumed that a series of data conversions have been completed and the process branches to the conversion procedure photon processing A. Note that when the predetermined number of conversions has not been completed, the conversion value storage area 203 -1's address information and conversion count data are updated and returned to the conversion parameter save area 203-2.
PC201-1, PSW 2 Q that was evacuated to 3-3
1-2, each content of the general register offset 201-3 is restored to the original field Rr, and the conversion interrupt service is completed.

As explained above, in the software processing by interrupts in the conventional microcontroller, in addition to transferring A/D conversion values, C1) tJ interrupt processing pc, psw
, save general-purpose register to general-purpose register seat register,
In addition, many processes (overhead) such as returning from the stack register and returning to the main routine are necessary. This overhead occupies a considerable amount of all interrupt service routines, and this method also has the drawback of significantly reducing the amount of execution time that can be devoted to main processing, and reducing the overall processing capacity of the CPU. (I'm doing j.

Furthermore, it is conceivable to use a buffering method in which the first few registers equivalent to the Vc and CRR 109 are built in parallel, and an interrupt request is issued when A/D converted values are stored in all of these CRRs.

This means that by increasing the number of CRRs to 'ff:n, the number of interrupt occurrences per interrupt decreases to -9, which reduces the proportion of overhead associated with one interrupt, which is an advantage in terms of improving CPU execution efficiency. Although this is a significant improvement, increasing the number of CRRs provided as buffers leads to the disadvantage of increasing the chip surface of the microcombicouter.

As shown in Part 2, the data processing equipment A with a built-in conventional A/D converter has many problems with CPtJ (or the disadvantage of lowering the CPU processing power). - It suffers from one of the disadvantages of being uneconomical with the hardware II+I.

The purpose of the present invention is to reduce A without deteriorating the CPU processing capacity and with less hardware occupation i<ri tJj.
An object of the present invention is to provide a data processing device having a /D conversion processing function.

The present invention comprises an A/D converter that generates converted data and a variable IA photon signal upon completion of A/D conversion, and an execution unit (CPU) that performs all normal program processing and data transfer processing based on the converted photon signal. In the 11'1 information processing device, which is fully equipped with a memory section that stores all processing data and programs, the execution section can execute A/D change data transfer processing while retaining all intermediate states during normal program processing. A/D conversion data processing control means 41iii, A
/1) When the variable part generates the conversion photon No. 18, the execution part A/1] converts photon No. It is characterized by executing conversion data transfer processing.

According to the present invention, processing based on the I10 state request for A/D conversion completion, that is, data transfer processing between the CRR and the data memory, can be performed without intervening program processing (software). I can. This data 11t transmission (hereinafter referred to as automatic data transfer processing 11) is carried out by I
10 When a request occurs, the CPU stops the program processing that is being executed, and keeps the state of the CPU at that time (hereinafter referred to as status) and all data in its place.5
The CPU itself performs all automatic data transfer processing. Therefore, it is possible to effectively utilize the hardware for controlling the instruction execution that is normally used when executing GLODARAM, and to perform processing without additionally adding special hardware for automatic data transfer processing. When the CPU completes the data transfer process, the overhead described in i-1 is calculated;
The status and data that were being drawn are restarted without interruption, and the execution of the program that was interrupted with L is resumed and continued. Therefore, the interruption of the program cannot be seen from the software, and it appears as if automatic data Ii5 and A[1 of the A/D transliteration data were automatically inserted during program processing. This automatic data transfer process allows software processing? Accompanying Al1) Frequency of conversion completion interrupts can be minimized, and CP
TJ o) Negative 4-1! It can be completely alleviated. -! Ta. As for the A/D variable rA jli' actually used,
] This is because the data that has been equalized by the Zanflink data calculation is used.

If you want to average the number of data you want to average, you can use the conventional interrupt method to handle the data you want to average.

Using Figure 4, we will explain below how this machine i) realizes two failures.
I'm going to hit the station]. A/D converter 40
0('It.

C1 C1. ? 400-2 pieces, I10 ideal control section 40
1, outputs an A/I) conversion completion signal 400-3. A/
The D conversion data processing control unit 500 includes the I10 request control unit 4
01. I10 processing execution request line 401-1 from there. I
10 processing processing type designation line 401-2 and CPU 510
The I10 hair request reception section 402 controls the operation of the I10 hair request reception section 402. On the other hand, the memory section includes a program memory 403 such as an interrupt processing program and an A/D conversion data storage area 404.
-1t data memory 404'fi-meet. Furthermore, the CPU 510 includes a PC 405-1 that indicates the address of the program to be executed next, an arithmetic and logic operation unit (hereinafter referred to as ALU) 206 that has an arithmetic and logic operation function, a PSW 405-2 that indicates the operating status of the entire CPU, and a PC 405-1 that indicates the address of the program to be executed next. General-purpose register set 405-3 for holding data. An instruction register 407 that holds the next instruction to be executed, an instruction decoder 408 that uses all contents of the instruction register 407 and generates various control signals, and outputs from the instruction decoder 408! IcPU
It includes an execution control unit 409 that controls the overall operation. Also,
A part of the data memory 404 is provided with an automatic transfer register group 440 necessary for automatic data transfer processing. This automatic transfer register 2! 'f404 fd, memory pointer (hereinafter referred to as MP) 440-J that specifies the address of the data memory, SFR pointer (hereinafter referred to as 5FRP) 440-2 that specifies the address of the special register. A
It includes a terminal counter (hereinafter referred to as TC) 440-3 that holds the number of times of /D conversion value automatic data transfer. All of the above functional elements are connected to an internal bus 410 and configured to allow data transfer between them.

Referring to this block diagram, the operation of automatic data transfer processing in A/DI conversion data processing will be described below.

All analog inputs 400-1 are sampled by the A/D converter 400, and the sampled A/D converted values are converted to CRR.
When stored in 400-2, A/D rabbit 1 completion signal 40
0-3 is output to the I10 request lighting control 1j1 section 401. I
In response to this, the I10 request control unit 401 accepts the I10 request via the I10 processing request line 401- connected to the unit 402.
1 and I10 processing mode, a signal is sent through the toe line 401-2. Detecting that the I10 processing request line 401-1 is active, the I10 request receiving section 402 samples the level of the I10 processing type finger/toe line 401-2 in the same town, and if this is a low level, this I10 request line 401-1 is active. The request is recognized as interrupt processing, and an interrupt processing code is set in the instruction register 407. 1, the execution control unit 409 executes the
05-1 address history r completely prohibited%PC405-1
, PSW405-2, general-purpose register set 405-3
The value of is saved in the data memory 404. Next, I1
0'A2 ice control unit 401 connects A/A2 on internal bus 410.
I) Output the branch at L/S of the conversion interrupt program,
The execution control unit 409 uses this ν, the branch address tPc
405-1, the A/D conversion interrupt processing program is activated. When this interrupt service program ends "j", the data that had been retired from the data memory 404Vc is transferred to the PC 405-1, PSW 405-2. The general-purpose register server) 405-3 is returned to, and the program processing whose execution was interrupted is resumed.

On the other hand, when the I10 processing execution mode designation 14401-2 is detected to be at a high level, the 10 processing reception section 402 recognizes that this I10 request is for an automatic data transfer device.

All automatic data transfer processing codes are set in the instruction register 407. The execution control unit 409 prohibits updating of the PC 405-1, and stores the values of the PC 405-1, PSW 405-2 and the general-purpose register set 405-3 in the data memory 404 (domain i). The process shown below is started as it is.First, the I10 request control unit 40
1 outputs all addresses of the automatic transfer register group 440 onto the internal bus 410, and the execution control unit 409 reads the addresses of the automatic transfer register group 440. Next, the execution control unit 40
9 is 5FRP440-2 of automatic transfer register group 440
A/D conversion value k lj from CRR400-2 indicated by
C protrudes.

Store this data in the A/D conversion 1-storage area 404-1 of the data memory 404 pointed to by the second MP440-1,
Calculate the value of TC440-3 by 1# and calculate TC440-3 again.
Store it in With the above series of processes, one automatic data transfer process in A/D transfer is completed. TC440-
When the value of 3 becomes '/l't'f41, p0+c, it is assumed that a series of data transfers have been completed, and all A/D converted values at this time are transferred to the A/D converted value storage area 404-1. After storing, the process 10 request control unit 401 activates the I10 processing fee request f;'I 401-1 again.
In #, set the process execution mode designator 401'-2 to low level and change the A/D @! When all the battles occur, I start up the A/D Hentai Interrupt Progera l-.

(-t A
/ Normal software interrupt processing and automatic data transfer processing are performed when the ZF photon issue occurs due to the completion of D conversion. In particular, when performing automatic data transfer processing, the PC 405 required for conventional KLI processing can be used.
-1, PSW405-2. Saving processing of general-purpose register 405 3 1 The time used for branch processing to interrupt programs, register restoration processing, instruction extraction, decoding, etc. can be significantly reduced, and the decline in CPU processing capacity can be minimized. It is possible to suppress it. Furthermore, the effect of the upper 81'J can be achieved without significantly increasing the total amount of dounia).
ζ, and can be done.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a conventional A/D converter, Figure 2 is light A.
/' A simple block diagram showing a conventional example of a microcomputer with a built-in D converter; Figure 3 is a flowchart of the conversion process from Figure 2; Figure 4 is an example of the present invention;
(This is a detailed block diagram of a microcomputer that performs the self-tjt data transfer function according to one example. 100...Conventional A/D converter, 101-1~
101-8...Analog input% 102...
...Multiplexer, 103...A/D channel mode register, 103-1...Channel designation pit. 103-2...A/D conversion completion flag, 104
...Sandals-kai hold circuit, 105...
...Ladder resistance circuit set, 106...Voltage comparator, 107...Successive approximation register (SPR)
), 108...controller, 109...
... Conversion result register (CR)? Enter 110...
CPU internal bus %200...Conventional microcomputer, 201...ri"h'nL 202
...Program memo 1c 203...
data memory. 203-1...Conversion value storage area, 203-2
・・・・・・Conversion bar make evacuation area j formation, 203-3・
...Stack area, 204...A/D converter, 204-1...Analog input, 204-
2...CRR1205...Internal bus,
206...1 shaving section including A/DV'+1, 210...Conversion completion signal, 210...
・Interrupt field request signal, 400...A/D converter, 4.00-1...Analog input, 400-2
・・・・・・'! , 400-3.
・・・・・・A/D fence; Completion signal, 401...
・E10 request! ij! I-bu, 401-1...
I10 Process execution request, 401-2...I10
Treatment rI! ! Execution form g repulsion designation line, 402...I1
0 Hair request reception section, 403...Program memory, 404...Data memory, 404-1...
... A/D conversion f direct area;, 405-J...
...Program memo 1c, 405-2...Program restorer status word% 405 3...
General purpose register set, 406...ALU, 4(
17...Instruction register% 408...
Instruction decoder, 409...Execution control unit, 410
...Internal bus, 440...Automatic transfer register group, 440-1...MP. 440-2...5FRP440-3...
・TC. 500...A/D conversion data processing control unit, 51
0...cpu. Y・1 し I ￥2 し■ Mostly diagram

Claims (1)

[Claims] and a central processing unit that selectively executes processing based on the conversion completion signal and processing according to the program; A/D conversion data processing control means capable of transferring the conversion data while maintaining a state in the middle of execution of the program, and when the A/D conversion processing section generates the conversion completion signal, the program An information processing apparatus characterized in that execution is interrupted and the A/D conversion data processing control means performs conversion data transfer processing.