JPS59226925A - Buffer controller - Google Patents

Abstract

PURPOSE:To perform high-speed DMA writing by providing a free area control circuit, interruption request circuit, and load control circuit in one buffer controller, and controlling the loading of DMA information and interruption information. CONSTITUTION:The DMA writing and interruption information is stored in a buffer memory circuit 12 and transferred to a data controller 30 through an interface circuit 16 successively. A loading control circuit 13 sends a load signal to the memory circuit 12 through a signal line (d) according to a load propriety signal sent from the free area control circuit 14 through a signal line (e) and a load propriety signal sent from the interruption request circuit 15 through a signal line (f) and execute a load indication. The control circuit 13 returns an answer to the 1st, 2nd, or 3rd input/output controllers 50, 60 or 70 through an interface circuit 11 so as to end a bus cycle with a bus answer signal on a signal line (e) after data is loaded into the memory 12 or when the load propriety signal is sent from the interruption request circuit 15.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a buffer control device in a data processing system, and more particularly to its D M A "J interrupt operation and interrupt processing.

(Prior art) Buffer memory IJ fl is generally used to absorb the difference in transfer speed between input and output, but when performing DMA write transfer from multiple input/output control devices via one buffer memory device, At the end of DMA, an interrupt request is generated from the input/output control device. In this case, after all DMA information has been transferred to the main storage device, the buffer control device sends an interrupt request to the interrupt processing device. The interrupt processing device sends a signal indicating that the acceptance is possible, and when the request rail is higher than the running level, the input/output control device is notified that the acceptance has been successful. On the other hand, a signal indicating that the acceptance is not possible is sent out, and when the required level is lower than the running level, the input/output control device is notified that the acceptance is unsuccessful and is prompted to request an interrupt again. In a series of these processes, if you wait to send an interrupt request until all DMA information has been transferred to the main memory, the effect of buffering as a means for waiting will be small, and in addition, the throughput will decrease. There was a drawback to that.

(Objective of the Invention) The object of the present invention is to use the interrupt level of the interrupt information when an interrupt request is received from the human output control device while loading DMA information into the buffer memory. , sends an interrupt request to the interrupt processing device. If the interrupt can be accepted, the interrupt information is loaded into the buffer memory, and if not accepted, it is not loaded and the interrupt is sent to the human output control device again. As soon as the buffer memory becomes free by prompting a request, multiple pieces of DMA write information are loaded, and interrupt information is loaded so as not to precede the end of DMA, thereby allowing DMA write information from multiple input/output control devices to be loaded. and interrupt information sequentially, resulting in high-speed DMA! An object of the present invention is to provide a buffer control device configured to realize a buffer control device.

(Structure of the Invention) In the buffer control device according to the present invention, one terminal is connected to a common bus together with a plurality of input/output control devices, and the other terminal is connected to a data control device connected to a central processing unit and a main storage device. This is a system configured to perform DMA write transfers between multiple input/output controllers and the main memory, and send interrupt requests from the input/output controllers to the central processing unit. It is used.

A buffer control device according to the present invention includes a buffer memory circuit, an empty area management circuit for managing empty areas of this buffer memory circuit, and a
M A It is equipped with an interrupt request circuit for accepting an interrupt request due to the end of a write transfer and sending the interrupt request to the central processing unit, and a load control circuit for controlling the load to the buffer memory circuit. be.

The buffer memory circuit is for storing DMA write information including addresses and data from multiple input/output control devices, and interrupt information including device numbers and interrupt levels from multiple input/output control devices. It is.

The empty area management circuit manages the empty area of the buffer memory using the empty area display signal sent from the buffer memory circuit, and sends an empty area presence/absence signal indicating the presence or absence of an empty area to the interrupt request circuit. This is for sending a first load permission/disapproval signal to the control circuit.

The interrupt request circuit receives DMA from multiple input/output control devices.
When an interrupt request due to the end of write transfer is accepted and an empty area presence/absence signal is received from the empty area management circuit, if the empty area presence/absence signal indicates presence, the interrupt level of the interrupt information (2) is set. This is used to send an interrupt request to the central processing unit, receive an interrupt permission signal from the central processing unit, and send a second load permission signal to the load control circuit. .

If the first load permission/prohibition signal sent from the empty area management circuit indicates permission, the load control circuit controls the DM
A@Output control number 18 indicating that the interrupt information is to be loaded to the buffer memory circuit, and when the second load permission signal output from the interrupt request circuit indicates permission, load the interrupt information. This is for outputting a control signal indicating this to the buffer memory circuit and responding to the common bus to terminate the bus cycle.

(Example) Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 shows the positioning of a buffer control device according to the present invention in a system. In FIG. 1, a buffer control device 10 and first to third input/output control devices [50,
60 and 70 are connected by a common bus 100, the central processing unit 20 and the main storage device 40 are connected to the data control device 30 by respective buses 300 and 400, and the buffer control device 10 and the data control device 30 is connected to the bus 200. The first to third input/output control devices 50, 60, and 70 each perform DMA transfer to the main storage device 40 via the buffer control device 10, and send interrupt requests to the central processing unit 20. I can do it.

FIG. 2 is a block diagram showing an embodiment of the buffer control device according to the present invention. In FIG. 2, the buffer control device includes first and second interface circuits 11
j16, buffer memory circuit 12, load control circuit 13, empty area management circuit 14, and 1 interrupt request circuit 15
It is constructed by comprising the following.

In FIG. 2, a first interface circuit 11 is connected to a common bus 100 and is connected to an input/output control device! 50,60.
This is for interfacing with 70 and the like. The second interface circuit 16 is connected to the bus 200 and is used to interface with the data control circuit 30.

In FIG. 2, DMA write information and interrupt information are stored in a buffer memory circuit 12 and sequentially transferred to a data control device 30 via a second interface circuit 16. The load control circuit 13 receives a first load permission signal sent from the empty area management circuit 14 via the signal line e and a second load permission signal sent from the 1 interrupt request circuit 15 via the signal if. The buffer memory circuit 12 sends a load signal to the buffer memory circuit 12 via the signal line d to issue a load instruction. After loading data into the load control circuit 13Fi buffer memory circuit 12 or when the second load enable/disable signal is sent from the interrupt request circuit 15, the bus cycle is terminated by the bus response signal on the Iri signal line C. First interface circuit 1
1 to the first, second, or third input/output control device 50°60.70.

Next, the operation will be explained based on the operation flow of the buffer control device 10 shown in FIG. 3 and the conceptual diagram of buffering shown in FIG. 4.

First, the A L sent out from the first input/output control device 5o
It is assumed that a DMA write operation of information up to -A n is started, and then a DMA write operation of information B+-Bnt sent from the second input/output control device 60 is started at an arbitrary time. Until an interrupt occurs, if the empty area management circuit 14 finds that there is an empty area in the buffer memory circuit 12, the load control circuit 13
DMA write information is loaded from the interface circuit 11 to the buffer memory circuit 12 via the signal line. On the other hand, the buffer memory circuit 12H sequentially sends DMA information to the signal line via the second interface circuit 16 and transfers it to the main storage device 40. in this case,
A2 to An and Bl to BnU are transferred according to the order of arrival. Assuming that the first input/output control device 50 has finished the DMA transfer and requested IN-TERRUPT, data control is performed according to the interrupt information on the interrupt request circuit 1sFi signal line and the interrupt level on the signal fflAg. An interrupt is made to the device 30 and a request is made. The data control device 3o compares the current driving level with the requested level, and sends a signal indicating that the acceptance of the interrupt response is possible via the signal line 200, indicating that the acceptance of the interrupt response is possible. Sky area management circuit 14
If the empty area presence/absence signal, which is not always sent via the signal line i, indicates empty, the interrupt request circuit 15 sends a load signal to the load control circuit 13 via the signal line f, indicating that loading is possible. Send a permission signal and load the interrupt information on signal ib 1.However, if the signal above the signal line indicates that interrupt response reception is not possible, the running level request is low. Therefore, you need to request it again. Therefore, the interrupt information is not loaded, and a pass response is sent back via the signal line C to the first input/output control device 50 again to prevent the occurrence of an interrupt. If the empty area presence/absence signal on signal line 1 indicates no area, loading is made to wait until it becomes available. If the empty area presence/absence signal on signal line i indicates nothing, DM A
The loading of write information and interrupt information is made to wait, and the common bus 100 remains locked. Main storage device 40
Since the transfer capacity of the common bus 100 is higher than that of the common bus 100, the probability that the common bus 100 is apparently locked during this lock time is very small.

D of information Bl to Bn from the second input/output control device 60
The interrupt processing after the MA write is completed is also the same as that of the first input/output control device 50, so a description of the operation will be omitted.

Since the interrupt request occurs at the end of DMA, the output from buffer memory circuit 12 must be in the correct order. Furthermore, interrupt requests generated from the first or second input/output control device 50, 60 must be processed in the order of arrival. Therefore, the timing of data passing to the buffer memory circuit 12 is the same as the timing of passing data to the common bus 100. Fortunately, the buffer memory circuit 12 does not distinguish between the first and second input/output control devices 50, 60, and can also receive input from the third input/output control device 10, and can also pass interrupt signals. Acceptance can be arbitrarily controlled not only during DMA writing but also from other input/output control devices such as general attention interrupts. On the other hand, since the level of the interrupt accepted from the interrupt request circuit 15 is higher than the current running level, the data control device 30 notifies the interrupt request circuit 15 that acceptance is possible, and then the actual interrupt information is transmitted through the signal line. The time it takes for the data to pass through the buffer memory circuit 12 and be transmitted from the second interface circuit 16 to the data control device 30 depends on the transfer speed between the buffer memory circuit 12 and the main memory device @40. do. However, this transfer rate Fi,
Since the transfer rate is higher than the transfer rate of the first and second input/output control devices 50 and 60, there is little effect on the time required for interrupt processing.

(Advantageous Effects of the Invention) As explained above, the present invention installs and combines an empty area management circuit, a 0 interrupt request circuit, and a load control circuit inside one buffer fti control device, thereby controlling the DMA information. By controlling the loading of DMA and interrupt information, it is possible to order multiple high-speed DMA writes and interrupt requests and achieve buffering without reducing system throughput. There is.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a processing system using a buffer control device. FIG. 2 is a block diagram showing the configuration of an embodiment of the buffer control device according to the present invention. FIG. 3 is a flowchart showing an example of the operation of the buffer control device shown in FIG. FIG. 4 is a conceptual diagram showing an example of buffering by the buffer control device shown in FIG. 2. 10...Buffer control circuit 20...Central processing circuit 30...Data control device 40...9 Main storage device 50.60.70...Input/output control device 11.16''
e-interface circuit 12--buffer memory circuit 13-control/load control circuit 14--empty area management circuit 15--interrupt request circuit 100, 200, 300, 400, @e bus a-m...
・Signal line patent applicant: NEC Corporation Representative, Patent attorney: Hisashi Inoro

Claims (1)

[Claims] One terminal is connected to a common bus together with a plurality of input/output control devices, and the other terminal is connected to a data control device connected to a central processing unit and a main memory, and the plurality of input/output control devices and the main memory are connected to each other. A buffer control device used in a system configured to perform DMA@inclusive transfer with a device and send interrupt requests from the plurality of input/output control devices to the central processing unit, DMA write information including addresses and data from the plurality of input/output control devices, 0, the 'rE, devices qi and 'r from the Tsuru input/output control devices, and interrupt information including the interrupt level. A buffer memory circuit for storing data and an empty area display signal sent from the buffer memory circuit to manage the empty area of the buffer memory circuit, and output an empty area presence/absence signal indicating the presence or absence of an empty area. an empty area management circuit that outputs a first load permission/disapproval signal; and an empty area management circuit that receives an interrupt request from the plurality of input/output control devices upon completion of the DMA@input transfer, and receives an interrupt request from the empty area management circuit. When the presence/absence signal is received, if the empty area presence/absence signal indicates presence, an interrupt request is sent to the central processing unit using the interrupt level in the interrupt information, and the central processing unit The interrupt request circuit receives a permission signal and outputs a second load permission signal, and the first load permission signal output from the empty area management circuit indicates permission. Sometimes said D
A control signal indicating that the MA@include information is to be loaded is sent to the buffer circuit, and when the second load permission signal output from the interrupt request circuit indicates yes, the control signal is sent to the buffer circuit. , a load control circuit for sending a control signal indicating that the interrupt information is to be loaded to the buffer memory circuit, and responding to the common bus to terminate the bus cycle. A buffer control device characterized by: