JPS60182480A - Scrambler - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a scrambler that scrambles digital data.

(Prior art and its problems) As a method of scrambling digital data, random numbers are generated and the random numbers are added to the digital data by 2.
A method of adding modulo is often used. In this case, conventional methods can be divided into two types: those in which the random number depends only on the initial value, and those in which the random number depends on the scrambled digital data. However, the method that relies only on the initial value has the disadvantage that the same random number is always generated after the initial value is set, so that the random number is easily exposed to a third party. On the other hand, in the method that relies on scrambled digital data, if the original digital data has periodicity, the scrambled digital data also has periodicity;
In the case of binary image transmission, the disadvantage is that it is possible to infer the original information even from scrambled digital data, or if an error occurs during transmission, the error will have long-lasting effects after decoding. It has the disadvantage of

It is about providing.

(Structure of the Invention) According to the present invention, a scrambler for scrambling digital data includes pattern generating means for generating a digital pattern depending on a predetermined key pattern, and a scrambled digital pattern as described below.
storage means for storing a predetermined amount of data in order from the newest data; a comparator for comparing the values of the pattern generation means and the storage means; and input digital data and the comparator. A scrambler is obtained which is characterized by comprising an exclusive OR circuit which outputs scrambled digital data from the output of the .

(Example) The operating principle of the present invention will be explained in detail below using diagrams showing examples.

For simplicity, it is assumed that the digital data is expressed in binary, and that the random number sequence is a sequence of 1 bit and 1 bit.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In the figure, a shift register 103 sequentially stores binary data output from an exclusive OR circuit (described later) bit by bit, and a pattern generator 102 generates a binary pattern depending on a key pattern from an input terminal 106. Output. A comparator 104 compares the outputs of the shift register 103 and the pattern generator 102 and outputs O or I.

The exclusive OR circuit 105 outputs the exclusive logical sum of the output of the comparator 104 and the binary data from the input terminal 107.

FIG. 2 is a block diagram showing an example of a device for decoding data scrambled by the device of the present invention. Second
The figure is a reverse version of Figure 1 except for the connections between some components. 202 and 102, 203 and 103, 204 and 104, and 205 and 105 have the same function. It is something to do.

In FIG. 2, the shift register 203 has an input terminal 207.
The ti-order storage pattern generator 202 outputs a binary pattern from the input terminal 206 depending on the binary data ti-th key pattern. Comparator 20
4 compares the outputs of the shift register 203 and the pattern generator 202 and outputs 0 or l. The exclusive OR circuit 205 outputs the exclusive OR of the output of the comparator 204 and the binary data from the input terminal 207.

When the device of the present invention is installed on the transmitting side and the device shown in Fig. 2 is installed on the receiving side, the binary data is scrambled by the device of the present invention and restored to the original binary data by the device shown in Fig. 2. shows. If the key patterns input to input terminals 106 and 206 are the same, pattern generators 102 and 202 will generate the same binary pattern.

At a certain point during operation, shift registers 103 and 2
The contents of 03 are the same binary data that are both scrambled. Also, both pattern generators 102 and 202 generate the same binary pattern. Therefore, the inputs of the same comparators 104 and 204 are the same,
The output will also be the same. Add the same binary number to binary data by 2
If the modulus is added twice, the original binary data is restored. Therefore, if the apparatus of the present invention and the apparatus shown in FIG. 2 are installed on the sending and receiving sides, respectively, the binary data will be restored by the apparatus of the present invention.

Also, is there an error on the shift register 203? Even if this occurs, it is only stochastic that this effect appears in the output of the comparator 204. Normally, the expansion of a 1-bit error can be suppressed to about 2 bits, so the influence of error propagation is small. Also, the shift register 103
Since the effect of the above pattern appears stochastically, the periodicity that occurs in the output due to the generation of the periodic pattern is eliminated.

The pattern generator 102 can be composed of, for example, a linear feedback shift register, and its connection state is determined by a key pattern (for linear feedback shift registers, see
Iwadare, Imai, "Coding Theory", Satoru Akimi, published 1973, 1
(See pages 21-135).

The initial value of the shift register can be determined in accordance with a protocol established between transmission and reception, fixed at the beginning, or changed using a synchronization code.

The comparator can be constructed by regarding each output of the shift register and a plurality of outputs of the pattern generator as multivalued signals, performing subtraction between the two signals, and outputting the sign thereof.

(Effects of the Invention) As explained above in detail, by using the present invention, the error υ propagation can be reduced, and since the periodicity can be eliminated for periodic digital data, it can be easily understood by a third party. Digital data can be scrambled so that it is difficult to be noticed, and it is extremely effective when used in a communication system.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram scrambled by the apparatus of the present invention. In the figure, 102 and 202 are pattern generators. 103 and 203 are shift registers, 104 and 204 are comparators, and 105 and 205 are exclusive OR circuits. 71 Figure O 2 Figure 202 203

Claims (1)

[Claims] Scrambler that scrambles digital data
, a pattern generating means for generating a digital pattern depending on a predetermined key pattern; and a memory for storing a predetermined amount of data in order from the newest data among the already scrambled digital data. a comparator for comparing the values of the pattern generation means and the storage means; and an exclusive OR circuit for outputting scrambled digital data from the input digital data and the output of the comparator. A scrambler characterized by