CA1211521A - Cryptographic system - Google Patents
Cryptographic systemInfo
- Publication number
- CA1211521A CA1211521A CA000432746A CA432746A CA1211521A CA 1211521 A CA1211521 A CA 1211521A CA 000432746 A CA000432746 A CA 000432746A CA 432746 A CA432746 A CA 432746A CA 1211521 A CA1211521 A CA 1211521A
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- Prior art keywords
- binary digits
- sequence
- responsive
- adder
- modulo
- Prior art date
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Abstract
"Cryptographic System"
ABSTRACT
A cryptographic system comprises a modulo-2 adder having a first input receptive of a sequence of binary digits to be scrambled and a second input receptive of a sequence of scrambling binary digits for generating a sequence of scrambled binary digits. A function generator having a memory is provided for storing a predeterminable sequence of binary digits in addressible storage locations and reading the stored binary digits in response to an address code represented by combined first and second patterns of binary digits which are generated respectively by a random pattern generator and a shift register which is connected to the output of the modulo-2 adder. The output of the function generator is the scrambling binary digits applied to the modulo-2 adder.
ABSTRACT
A cryptographic system comprises a modulo-2 adder having a first input receptive of a sequence of binary digits to be scrambled and a second input receptive of a sequence of scrambling binary digits for generating a sequence of scrambled binary digits. A function generator having a memory is provided for storing a predeterminable sequence of binary digits in addressible storage locations and reading the stored binary digits in response to an address code represented by combined first and second patterns of binary digits which are generated respectively by a random pattern generator and a shift register which is connected to the output of the modulo-2 adder. The output of the function generator is the scrambling binary digits applied to the modulo-2 adder.
Description
TITLE OF THE INVENTION
"Cryptographic System"
BACKGROUND OF THE INVEM~ION
The present invention relates to a cryptographic system.
When scrambling digital information data, it is the current practice to employ a random number generator which generates a random pattern of binary l's and O's with which the data are muddle summed. Current random number generators are broadly classified into a first type in which the random number is dependent exclusively on the initial value and a second type in which the random number is dependent on the scrambled data. The first type of random number generators it susceptible to wire tapping because the repetitive sequence of bit pattern is easily discernible by eavesdroppers. The second type of prior art scramblers comprises a shift register coupled to the output of a muddle adder which combines input data with the output of a cipher memory which stores a sequence of binary digits as a key code and reads the stored bits in response to an address code supplied from the shift register. The descrambler used in conjunction with such scramblers also comprises a shift register that supplies an address code for addressing the same key pattern as in the scrambler stored in a decipher memory the output of which is coupled to a muddle adder to be combined with the scrambled input data. Should a bit error occur in the transmitted sequence, decoded data will be disrupted and such disruption will continue as long as the error bit is shifted in the shift register. If the number of the shift resister stages is substantial, the disruption will continue for a long period of time even ire the disruption is caused by a single bit error.
SUMMARY OF THE INVENTION
-It is therefore an object of the invention to provide a cryptographic system which prevents long-period data disruptions while ensuring security against eavesdroppers.
This object is obtained by combining the non repetitive characteristic of feedback random number generation and the repetitive characteristic of initial key pattern generation to form a combined address code with which stored bits of the key pattern are addressed for muddle summation with information data bits A cryptographic system of the present invention comprises a data scrambler connected to one end of a medium for transmission of scrambled binary digits through said medium and a data descrambler connected to the other end of the medium to receive the-transmitted binary digits. The data scrambler comprises a first muddle adder having a first input connected to be responsive to a sequence of binary digits to be scrambled and a second input connected to be responsive to a sequence of scrambling binary digits for generating a sequence of scrambled binary digits for application to the medium A first function generator having a memory is provided four storing a predeterminable sequence of binary digits in addressable storage locations and reading the stored binary digits in response to an address code represented by combined first and second patterns of binary digits which are generated respectively by a first pattern generator and a first shift register which is connected to the output of the first muddle adder. The output of the first function generator is the scrambling binary digits applied to the first muddle adder.
The data descrambler comprises a second oddly adder having a first input connected to be responsive to the received binary digits and a second input connected to be responsive to a sequence of descrambling binary digits for generating a sequence of descrambled binary digits. A
second function generator having a memory is included for storing a predeterminable sequence of binary digits in addressable storage locutions and reading the stored binary digits in response to an address code represented by combined random patterns of binary digits which are generated respectively a second random pattern generator and a second shift register which is connected to be responsive to the received binary digits. The output of the second function generator is the descrambling binary digits applied to the second muddle adder.
In the event of a transmission error, a disruption will occur in the bit stream in the second shift register.
However, the disruption persists as long as the error bit exists in the second shift register which accounts for only a portion of the full address code of the second function generator. Therefore, the cryptographic system of the invention has a smaller disruption time than that of the second type of prior art while eliminating the disadvantage of the first type of prior art.
ROUGH DESCRIPTION OF_ THE DRAWINGS
The present invention will be described in further detail with reference to the accompanying drawings, in which:
Fig. 1 is a schematic illustration of a preferred embodiment of the invention; and Fig. 2 is an illustration of an alternative embodiment of the invention.
DETAILED DESCRIPTION
Referring now to Fig. 1, there is shown a cryptographic system of-the present invention. The system . 5 generally comprises a data scrambler lo and a data descrambler I connected over a transmission medium OWE
The data scrambler 10 comprises a function generator 11, a key pattern generator 12, a random pattern generator 13, a shift register 14 and a muddle adder or Exclusi~e-OR gate 15. The function generator 11 may comprise a read-only memory or random access memory for storing a random sequence of binary l's and 0's supplied from the key pattern generator 12 in addressable locations. The random pattern generator Lo may comprise a linear feedback shift register which generates a sequence of random patterns of parallel binary l's and 0's in response to a clock pulse supplied from a clock source 17. The function generator 11 reads the stored binary l's and 0's as a function of an address code which combines the outputs of the random pattern generator 13 and shift register 14. The output of the function generator 11 is therefore a random sequence of scrambling binary l's and 0's which are fed to the muddle adder 15. A sequence of input digital data at input terminal 16 is muddle summed in the adder 15 with the scrambling bits on a per bit basis. The scrambled data bits are sequentially applied on the one hand to the shift register 14 and on the other hand to the transmission medium 30~ The shift register 14 supplies the stored bits to the function generator 11 in parallel form in response to the clock pulse supplied from the clock source 17 which is synchronized with the input digital data. The function generator 11 is also synchronized with the clock source 17 so that the scrambling data bits are time coincident with the input data bits at terrlinal 16.
The transmitted scrambled data bits are received by the data descrambler 20. The descxambler 20 operates on the received data bits in a process inverse to that of the scrambler 10. The scrambled data bits are applied to a shift register 24 having the same number of bit positions as the shift register 14. A function generator 21 identical to the function generator if stores a key pattern supplied from a key pattern generator 22 and reads the stored bits as a function of a combined set of address bits supplied from the shift register 24 and a random pattern generator 23 which is also identical to the random pattern generator 13. A bit synchronization pulse is obtained from a sync generator 27 coupled to the input terminal of the descrambler. The input bit stream is muddle summed in an Exclusive-OR gate 25 with a sequence of descrambling bits from the function generator 21. The original bit stream is delivered from the muddle adder 25 to an output terminal 26.
Since the number of bits stored in the shift register 24 accounts for a fraction of the number of ,..
I
address bits and is much smaller than the corresponding number of bits of the feedback type of prior art cryptographic system, a bit error in the received sequence will exist in the shift register 24 for a small interval tire as compared with the prior art system, and the resultant disruption does not persist for a long period of time. Since the scrambled data sequence contains no repetitive patterns, the system ensures security against wire tapping.
Fig. 2 is an illustration of an alternative embodiment of the invention which is similar to the previous embodiment with the exception that in the scrambler 10 one of the output leads of the shift register 14 is disconnected from the function generator 11 and coupled instead to an input of a muddle adder 18. The muddle adder 18 takes its another input from the function generator 11 to provide a sequence of scrambling bits for coupling to the muddle adder 15. Alternatively, one of the output leads of the random pattern generator 13 may be disconnected from the function generator 11 and coupled to the module 2 adder 18, instead of applying the one-bit output from the shift register 14. In like manner, the descrambler 20 includes a muddle adder 28 which receives one of the output leads ox the shift register 24 to prove muddle summation with-the output of the function So.
generator 21 for generating a descrambling bit sequence for application to the muddle adder 25.
w
"Cryptographic System"
BACKGROUND OF THE INVEM~ION
The present invention relates to a cryptographic system.
When scrambling digital information data, it is the current practice to employ a random number generator which generates a random pattern of binary l's and O's with which the data are muddle summed. Current random number generators are broadly classified into a first type in which the random number is dependent exclusively on the initial value and a second type in which the random number is dependent on the scrambled data. The first type of random number generators it susceptible to wire tapping because the repetitive sequence of bit pattern is easily discernible by eavesdroppers. The second type of prior art scramblers comprises a shift register coupled to the output of a muddle adder which combines input data with the output of a cipher memory which stores a sequence of binary digits as a key code and reads the stored bits in response to an address code supplied from the shift register. The descrambler used in conjunction with such scramblers also comprises a shift register that supplies an address code for addressing the same key pattern as in the scrambler stored in a decipher memory the output of which is coupled to a muddle adder to be combined with the scrambled input data. Should a bit error occur in the transmitted sequence, decoded data will be disrupted and such disruption will continue as long as the error bit is shifted in the shift register. If the number of the shift resister stages is substantial, the disruption will continue for a long period of time even ire the disruption is caused by a single bit error.
SUMMARY OF THE INVENTION
-It is therefore an object of the invention to provide a cryptographic system which prevents long-period data disruptions while ensuring security against eavesdroppers.
This object is obtained by combining the non repetitive characteristic of feedback random number generation and the repetitive characteristic of initial key pattern generation to form a combined address code with which stored bits of the key pattern are addressed for muddle summation with information data bits A cryptographic system of the present invention comprises a data scrambler connected to one end of a medium for transmission of scrambled binary digits through said medium and a data descrambler connected to the other end of the medium to receive the-transmitted binary digits. The data scrambler comprises a first muddle adder having a first input connected to be responsive to a sequence of binary digits to be scrambled and a second input connected to be responsive to a sequence of scrambling binary digits for generating a sequence of scrambled binary digits for application to the medium A first function generator having a memory is provided four storing a predeterminable sequence of binary digits in addressable storage locations and reading the stored binary digits in response to an address code represented by combined first and second patterns of binary digits which are generated respectively by a first pattern generator and a first shift register which is connected to the output of the first muddle adder. The output of the first function generator is the scrambling binary digits applied to the first muddle adder.
The data descrambler comprises a second oddly adder having a first input connected to be responsive to the received binary digits and a second input connected to be responsive to a sequence of descrambling binary digits for generating a sequence of descrambled binary digits. A
second function generator having a memory is included for storing a predeterminable sequence of binary digits in addressable storage locutions and reading the stored binary digits in response to an address code represented by combined random patterns of binary digits which are generated respectively a second random pattern generator and a second shift register which is connected to be responsive to the received binary digits. The output of the second function generator is the descrambling binary digits applied to the second muddle adder.
In the event of a transmission error, a disruption will occur in the bit stream in the second shift register.
However, the disruption persists as long as the error bit exists in the second shift register which accounts for only a portion of the full address code of the second function generator. Therefore, the cryptographic system of the invention has a smaller disruption time than that of the second type of prior art while eliminating the disadvantage of the first type of prior art.
ROUGH DESCRIPTION OF_ THE DRAWINGS
The present invention will be described in further detail with reference to the accompanying drawings, in which:
Fig. 1 is a schematic illustration of a preferred embodiment of the invention; and Fig. 2 is an illustration of an alternative embodiment of the invention.
DETAILED DESCRIPTION
Referring now to Fig. 1, there is shown a cryptographic system of-the present invention. The system . 5 generally comprises a data scrambler lo and a data descrambler I connected over a transmission medium OWE
The data scrambler 10 comprises a function generator 11, a key pattern generator 12, a random pattern generator 13, a shift register 14 and a muddle adder or Exclusi~e-OR gate 15. The function generator 11 may comprise a read-only memory or random access memory for storing a random sequence of binary l's and 0's supplied from the key pattern generator 12 in addressable locations. The random pattern generator Lo may comprise a linear feedback shift register which generates a sequence of random patterns of parallel binary l's and 0's in response to a clock pulse supplied from a clock source 17. The function generator 11 reads the stored binary l's and 0's as a function of an address code which combines the outputs of the random pattern generator 13 and shift register 14. The output of the function generator 11 is therefore a random sequence of scrambling binary l's and 0's which are fed to the muddle adder 15. A sequence of input digital data at input terminal 16 is muddle summed in the adder 15 with the scrambling bits on a per bit basis. The scrambled data bits are sequentially applied on the one hand to the shift register 14 and on the other hand to the transmission medium 30~ The shift register 14 supplies the stored bits to the function generator 11 in parallel form in response to the clock pulse supplied from the clock source 17 which is synchronized with the input digital data. The function generator 11 is also synchronized with the clock source 17 so that the scrambling data bits are time coincident with the input data bits at terrlinal 16.
The transmitted scrambled data bits are received by the data descrambler 20. The descxambler 20 operates on the received data bits in a process inverse to that of the scrambler 10. The scrambled data bits are applied to a shift register 24 having the same number of bit positions as the shift register 14. A function generator 21 identical to the function generator if stores a key pattern supplied from a key pattern generator 22 and reads the stored bits as a function of a combined set of address bits supplied from the shift register 24 and a random pattern generator 23 which is also identical to the random pattern generator 13. A bit synchronization pulse is obtained from a sync generator 27 coupled to the input terminal of the descrambler. The input bit stream is muddle summed in an Exclusive-OR gate 25 with a sequence of descrambling bits from the function generator 21. The original bit stream is delivered from the muddle adder 25 to an output terminal 26.
Since the number of bits stored in the shift register 24 accounts for a fraction of the number of ,..
I
address bits and is much smaller than the corresponding number of bits of the feedback type of prior art cryptographic system, a bit error in the received sequence will exist in the shift register 24 for a small interval tire as compared with the prior art system, and the resultant disruption does not persist for a long period of time. Since the scrambled data sequence contains no repetitive patterns, the system ensures security against wire tapping.
Fig. 2 is an illustration of an alternative embodiment of the invention which is similar to the previous embodiment with the exception that in the scrambler 10 one of the output leads of the shift register 14 is disconnected from the function generator 11 and coupled instead to an input of a muddle adder 18. The muddle adder 18 takes its another input from the function generator 11 to provide a sequence of scrambling bits for coupling to the muddle adder 15. Alternatively, one of the output leads of the random pattern generator 13 may be disconnected from the function generator 11 and coupled to the module 2 adder 18, instead of applying the one-bit output from the shift register 14. In like manner, the descrambler 20 includes a muddle adder 28 which receives one of the output leads ox the shift register 24 to prove muddle summation with-the output of the function So.
generator 21 for generating a descrambling bit sequence for application to the muddle adder 25.
w
Claims (9)
1. A cryptographic system comprising:
a data scrambler connected to one end of a medium, comprising:
a first modulo-2 adder having a first input connected to be responsive to a sequence of binary digits to be scrambled and a second input connected to be responsive to a sequence of scrambling binary digits for generating a sequence of scrambled binary digits for application to said medium;
a first pattern generator for generating a sequence of random patterns of binary digits;
a first shift register connected to be responsive to said scrambled binary digits for generating a sequence of random patterns of binary digits; and a first function generator having a memory for storing a predeterminable sequence of binary digits in addressible storage locations and reading the stored binary digits in response to an address code represented by combined random patterns of binary digits supplied from said first pattern generator and said first shift register for generating a sequence of binary digits for application to said first modulo-2 adder as said scrambling binary digits, and a data descrambler connected to the other end of said medium to receive said sequence of scrambled binary digits, comprising:
a second modulo-2 adder having a first input connected to be responsive to the received sequence of scrambled binary digits and a second input connected to be responsive to a sequence of descrambling binary digits for generating a sequence of descrambled binary digits;
a second pattern generator for generating a sequence of random patterns of binary digits;
a second shift register connected to be responsive to the received sequence of scrambled binary digits for generating a sequence of random patterns of binary digits;
and a second function generator having a memory for storing a predeterminable sequence of binary digits in addressible storage locations and reading the stored binary digits in response to an address code represented by combined random patterns of binary digits supplied from said second pattern generator and said second shift register for generating a sequence of said binary digits for application to said second modulo-2 adder as said descrambling binary digits.
a data scrambler connected to one end of a medium, comprising:
a first modulo-2 adder having a first input connected to be responsive to a sequence of binary digits to be scrambled and a second input connected to be responsive to a sequence of scrambling binary digits for generating a sequence of scrambled binary digits for application to said medium;
a first pattern generator for generating a sequence of random patterns of binary digits;
a first shift register connected to be responsive to said scrambled binary digits for generating a sequence of random patterns of binary digits; and a first function generator having a memory for storing a predeterminable sequence of binary digits in addressible storage locations and reading the stored binary digits in response to an address code represented by combined random patterns of binary digits supplied from said first pattern generator and said first shift register for generating a sequence of binary digits for application to said first modulo-2 adder as said scrambling binary digits, and a data descrambler connected to the other end of said medium to receive said sequence of scrambled binary digits, comprising:
a second modulo-2 adder having a first input connected to be responsive to the received sequence of scrambled binary digits and a second input connected to be responsive to a sequence of descrambling binary digits for generating a sequence of descrambled binary digits;
a second pattern generator for generating a sequence of random patterns of binary digits;
a second shift register connected to be responsive to the received sequence of scrambled binary digits for generating a sequence of random patterns of binary digits;
and a second function generator having a memory for storing a predeterminable sequence of binary digits in addressible storage locations and reading the stored binary digits in response to an address code represented by combined random patterns of binary digits supplied from said second pattern generator and said second shift register for generating a sequence of said binary digits for application to said second modulo-2 adder as said descrambling binary digits.
2. A cryptographic system as claimed in claim 1, wherein the number of binary digits in each pattern generated by each of said first and second shift registers is smaller than the number of binary digits in each random pattern generated by each of said first and second pattern generators.
3. A cryptographic system as claimed in claim 1, wherein said first shift register includes a first bit position and a plurality of second bit positions coupled to said first function generator, and wherein said scrambler further comprises a third modulo-2 adder having a first input connected to be responsive to said first bit position and a second input connected to be responsive to a sequence of binary digits supplied from said first function generator and providing a sequence of binary digits for application to said first modulo-2 adder as said scrambling binary digits, and wherein said second shift register includes a first bit position and a plurality of second bit positions coupled to said second function generator, said descrambler further comprising a fourth modulo-2 adder having a first input connected to be responsive to said first bit position of said second shift register and a second input connected to be responsive to a sequence of binary digits supplied from said second function generator for application to said second modulo-2 adder as said descrambling binary digits.
4. A data scrambler for cryptographic systems comprising:
a modulo-2 adder having a first input connected to be responsive to a sequence of binary digits to be scrambled and a second input connected to be responsive to a sequence of scrambling binary digits for generating a sequence of scrambled binary digits to be transmitted;
a pattern generator for generating a sequence of random patterns of binary digits;
a shift register connected to be responsive to said scrambled binary digits for generating a sequence of random patterns of binary digits; and a function generator having a memory for storing a predeterminable sequence of binary digits in addressible storage locations and reading the stored binary digits in response to an address code represented by combined patterns of binary digits supplied from said pattern generator and said shift register for generating a sequence of binary digits for application to said modulo-2 adder as said scrambling binary digits.
a modulo-2 adder having a first input connected to be responsive to a sequence of binary digits to be scrambled and a second input connected to be responsive to a sequence of scrambling binary digits for generating a sequence of scrambled binary digits to be transmitted;
a pattern generator for generating a sequence of random patterns of binary digits;
a shift register connected to be responsive to said scrambled binary digits for generating a sequence of random patterns of binary digits; and a function generator having a memory for storing a predeterminable sequence of binary digits in addressible storage locations and reading the stored binary digits in response to an address code represented by combined patterns of binary digits supplied from said pattern generator and said shift register for generating a sequence of binary digits for application to said modulo-2 adder as said scrambling binary digits.
5. A data scrambler as claimed in claim 4, wherein the number of binary digits in each pattern generated by said shift register is smaller than the number of binary digits in each random pattern generated by said pattern generator.
6. A data scrambler as claimed in claim 4, wherein said shift register includes a first bit position and a plurality of second bit positions coupled to said function generator, further comprising a second modulo-2 adder having a first input connected to be responsive to said first bit position and a second input connected to be responsive to a sequence of binary digits supplied from said function generator and providing a sequence of binary digits for application to the first-mentioned modulo-2 adder as said scrambling binary digits.
7. A data descrambler for cryptographic systems comprising:
a modulo-2 adder having a first input connected to be responsive to the received sequence of scrambled binary digits and a second input connected to be responsive to a sequence of descrambling binary digits for generating a sequence of descrambled binary digits;
a pattern generator for generating a sequence of random patterns of binary digits;
a shift register connected to be responsive to the received sequence of scrambled binary digits for generating a sequence of random patterns of binary digits; and a function generator having a memory for storing a predeterminable sequence of binary digits in addressible storage locations and reading the stored binary digits in response to an address code represented by combined patterns of binary digits supplied from said pattern generator and said shift register for generating a sequence of said binary digits for application to said modulo-2 adder as said descrambling binary digits.
a modulo-2 adder having a first input connected to be responsive to the received sequence of scrambled binary digits and a second input connected to be responsive to a sequence of descrambling binary digits for generating a sequence of descrambled binary digits;
a pattern generator for generating a sequence of random patterns of binary digits;
a shift register connected to be responsive to the received sequence of scrambled binary digits for generating a sequence of random patterns of binary digits; and a function generator having a memory for storing a predeterminable sequence of binary digits in addressible storage locations and reading the stored binary digits in response to an address code represented by combined patterns of binary digits supplied from said pattern generator and said shift register for generating a sequence of said binary digits for application to said modulo-2 adder as said descrambling binary digits.
8. A data descrambler as claimed in claim 7, wherein the number of binary digits in each pattern generated by said shift register is smaller than the number of binary digits in each random pattern generated by said pattern generator.
9. A data descrambler as claimed in claim 7, wherein said shift register includes a first bit position and a plurality of second bit positions coupled to said function generator, further comprising a second modulo-2 adder having a first input connected to be responsive to said first bit position and a second input connected to be responsive to a sequence of binary digits supplied from said function generator for application to the first-mentioned modulo-2 adder as said descrambling binary digits.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57126183A JPS5916441A (en) | 1982-07-20 | 1982-07-20 | Scrambler |
| JP57-126183 | 1982-07-20 | ||
| JP57126184A JPS5916442A (en) | 1982-07-20 | 1982-07-20 | Descrambler |
| JP57-126184 | 1982-07-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1211521A true CA1211521A (en) | 1986-09-16 |
Family
ID=26462406
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000432746A Expired CA1211521A (en) | 1982-07-20 | 1983-07-19 | Cryptographic system |
Country Status (2)
| Country | Link |
|---|---|
| AU (1) | AU569473B2 (en) |
| CA (1) | CA1211521A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| NL8602847A (en) * | 1986-11-11 | 1988-06-01 | Philips Nv | METHOD FOR Ciphering / Deciphering and Device for Carrying Out the Method |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1360260A (en) * | 1971-09-23 | 1974-07-17 | Standard Telephones Cables Ltd | Multilevel pcm system |
| NL7710503A (en) * | 1977-09-27 | 1979-03-29 | Philips Nv | DIGITAL TRANSMISSION SYSTEM. |
-
1983
- 1983-07-19 CA CA000432746A patent/CA1211521A/en not_active Expired
- 1983-07-19 AU AU16964/83A patent/AU569473B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| AU1696483A (en) | 1984-01-26 |
| AU569473B2 (en) | 1988-02-04 |
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