JPS60182157A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To effectively prevent the reaction generating between a semiconductor base layer and a metal layer by a method wherein an annealing is performed instantaneously on a high melting point metal silicide. CONSTITUTION:An MoSi2 film 11 is coated on the whole surface of a film whereon a PSG film 10 is covered allover. In the above-mentioned condition, boron is ion-implanted on the whole surface. Then, an annealing is performed instantaneously, i.e., for 10sec or thereabout for example, at the approximate temperature range of 900-1,000 deg.C. Said instantaneous annealing is performed in order to improve the film quality of the MoSi2 film, to activate the ion-implanted boron and to obtain an ohmic contact between the MoSi2 film 11 and p type regions 3 and 4.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, particularly a method for manufacturing a C-MOS (C-MOS).
complementary Metal Oxide
The present invention relates to a method for forming electrodes of a semiconductor device of the Sem1conductor type.

Prior Art and Problems The C-MO8 integrated circuit (IC) has the features of low power consumption and high speed, and its application and development are active. By the way, electrode formation for a C-MOS IC involves, for example, forming a p-type source region and a drain region in an n-type silicon substrate, forming a p-type well, and inserting an n-type source region and a drain region in the p-type well. A semiconductor body in which a drain region is formed,
After forming the gate electrode with polysilicon and completing all the electrode windows, aluminum (e.g. 1% silicon alloy) is formed.
The layers are deposited and patterned and then e.g.
It is annealed at .degree. C. to compensate for ohmic contact between aluminum and silicon. In this case, good ohmic contact is achieved in the p-shaded region and the polysilicon region (gate), but in the n-shaded region, there is a reaction between aluminum and silicon within the electrode window, especially due to the melting and re-precipitation of silicon during the annealing process. Perhaps because a p-type epitaxial layer is generated, the ohmic contact is not good, and this tendency is particularly noticeable when the electrode window becomes small.

Therefore, in order to prevent the reaction between the aluminum of the wiring layer and the silicon of the semiconductor body, it is known to provide a barrier layer between them.The barrier layer is made of high melting point metal silicide such as molybdenum silicide is used. However, a high melting point metal silicide layer that is conventionally formed by, for example, sputtering is in an amorphous phase and is unsuitable as a barrier layer because its constituent atoms have weak bonds.

Therefore, in order to make a stronger silicide film, for example, if annealing is performed for 20 minutes at 900 to 1000°C in a diffusion furnace, good ohmic contact can be achieved in all of the n-shade region, p-shade region, and IJ silicon region. There is a feeling of being unable to get rid of it.

On the other hand, the present inventors have found that, after forming a high melting point gold ingot silicide (amorphous phase) layer, if annealing is performed instantaneously (for example, for about 10 seconds) using, for example, a nitrogen lamp,
It has been found (unknown to the public) that ohmic contact can be made stably and with good reproducibility to the n-formation planned region and the polysilicon region (n-type). However, even with this method, the ohmic contact with the p-formation region is still not sufficient.
The purpose is to form good wiring (electrode) contacts in both the p-type semiconductor region and the n-type semiconductor region.

Structure of the Invention In order to achieve the above object, in the present invention, after depositing a high melting point silicide layer (barrier layer) on the p-type semiconductor region and the n-type semiconductor region, the p-type and n-type A step of ion-implanting p-type impurities into both semiconductor regions (including a single crystal region and a polycrystalline region) and performing annealing, as well as completely canceling out the ion implantation of the p-type impurities into the n-type semiconductor region. Therefore, when introducing an n-type impurity into a region where an n-type semiconductor region is to be formed, an extra predetermined amount corresponding to the amount of n-type impurity and gold p-type impurity implanted is introduced.

High melting point silicide layer (barrier layer) after applying this barrier layer
Through p-type impurity implantation and instantaneous annealing, the high melting point silicide is stabilized to effectively inhibit the reaction between the semiconductor base layer and the interconnect metal layer, and the high melting point silicide and both p-type and n-type semiconductor base layers are A good ohmic contact between the two is achieved. The purpose of implanting p-type impurities through the high melting point silicide layer before instantaneous annealing is to establish ohmic contact between the high melting point silicide layer and the p-type semiconductor region.
This should be done selectively only for semiconductor regions. However, in order to do this, seven patterning steps must be performed on the high melting point silicide layer only in the p-type semiconductor region, and then the resist will be applied after B+ implantation. A removal step is required, resulting in reduced throughput and yield. Therefore, in the present invention, a high melting point silicide layer? In order to implant the p-type impurity into the entire surface of the n-type semiconductor region rather than selectively, and to offset the influence of the p-type impurity implanted into the n-type semiconductor region, the p-type impurity is implanted into the n-type semiconductor region. Introduce extra impurities. The amount of increase in the amount of n-type impurity introduced should be determined experimentally in correspondence with the amount of p-type impurity implanted.

If the impurity concentration increases in the n-type semiconductor region and the diffusion length of impurities due to activation annealing is undesirably large, activation annealing may be performed by instantaneous annealing instead of diffusion furnace annealing.

In the present invention, the p-type or n-type semiconductor region to be formed in contact with the wiring metal layer via the barrier layer may be formed as a p-type or n-type region before the barrier layer is deposited. , or p-type or n-type after barrier layer deposition.
It may be formed by implanting an impurity in the form of p
The type semiconductor region may also be formed by the p-type impurity itself, which is implanted for contact compensation after the barrier layer has been deposited.

In the present invention, there are no particular limitations on the material of the semiconductor base layer, the type of impurities, the material of the wiring metal layer, etc., and high melting point metal silicides include molybdenum silicide, tungsten silicide, tantalum silicide, titanium silicide, etc.
be caught. As a method for inter-domain annealing, halogen lamp annealing, black body radiation heating, or the like may be used.

Embodiments of the Invention An embodiment in which the present invention is applied to a (-C-MUS) transistor will be described. Referring to FIG. The p-type source region 3 is in the region surrounded by
and p-type drain region 4 (respectively boron-doped, I
At the same time, a large p-type well (boron-doped 5 x 1013 cm-2) 5 is formed in another region surrounded by field oxide film 2, and an n-type source region 6 is formed therein. and n-type drain region 7 are formed. The n-type source region 6 and n-type drain region 7 are doped with arsenic 'i 8 × 10'' cm-.

The dose of arsenic in these regions 6 and 7 was 4×10 15 cm in the conventional case where p-type impurities were not implanted in a post process as in the present invention.

In this example, p is added to these regions 6 and 7 in a later process.
Since the type impurity is implanted at a dose of 4 x 1015crrV, these doses are added to the base to give 8X.
Select 10”cm-2 and ft.

On each of the p-type and n-type channels, a pole 9 is formed in polysilicon (phosphorous doped, 15Ω/2) with a gate oxide film 8 interposed therebetween.

Although the entire surface is covered by the PSG film 10, electrode films are opened in each of the source and drain regions 3, 4, 6.7, the acid film and the PSG film 1O directly above the gate electrode 9.

Referring to Figure 2, sputtering such as simultaneous sputtering type, hot press type, etc. can be used! A llMo5i2 film 11 is deposited to a thickness of about 30 nm over the entire surface. As mentioned earlier, this MoSi2 film 11 is in an amorphous phase.

In this state, boron is applied to the entire surface at an accelerating voltage of, for example, 70 keV.
, Ion implantation is carried out to a dose of, for example, 4X10"c-. Then, the ions are implanted at a dose of 900 to 10
Instantaneous annealing is performed at about 00° C. for about 10 seconds, for example. This instantaneous annealing is performed to improve the film quality of the MoSi2 film 11 and to fully activate the implanted boron to form ohmic contacts i between the MO8i2 film 11 and the film shadow regions 3 and 4.

If you refer to all of Figure 3, the aluminum layer (1% silicon)
(alloy) 12 is deposited on the entire surface and patterned including MoSi211i11 to form electrodes and distribution fff'FC. In this way, ohmic contact can be established between Mo S i 2 and p-type silicon. Aluminum and Mo
3 i 2 can make ohmic contact without any problems, and since the MoSi 2 film 11 is stable, the silicon under the MoSi 2 11 is prevented from reacting with aluminum, and the aluminum wiring and n Ohmic contact with the shadow area 6.7 or polysilicon is also good.

C-MUS Ict created in this way - Deterioration of the contact was observed under conditions of 500°C in a nitrogen atmosphere (accelerated test) 0 As a result, the n shadow area, p shadow area and n
Contacts were shown to be stable over long periods of time in both shaped polysilicon regions. Note that in the case of conventional aluminum (1% silicon alloy) wiring without a barrier layer, the contacts in the n-shaded area and n-type polysilicon area immediately deteriorate and become unusable in the same accelerated test.

Furthermore, according to this embodiment, ie, the method of the invention, M
The ion implantation of boron (p-type impurity) through o5x2@11f does not need to be performed selectively, but only needs to be performed over the entire surface. Therefore, one step of forming, patterning, and removing a mask such as a resist is no longer necessary.
As throughput increases, yield increases by one less alignment for mask patterning.

Although the contact resistance of the n-type source region 6 and the n-type drain region 7 increased somewhat compared to the case where no p-type impurity was implanted, the function as a transistor was sufficient. Optimum for H is the n-type sauce area @ 6 ↓
It is considered preferable to further increase the dose of arsenic (n-type impurity) to the n-type impurity region 7.

The above explanation has been given using an example of aluminum interconnection using a MoSiS film as a barrier layer on a silicon substrate. It will be appreciated that the present invention is applicable not only to the above examples but also generally. Processing conditions can also be changed as appropriate.

Effects of the Invention As is clear from the above explanation, the present invention makes it possible to form good ohmic contacts with both p-type and n-type semiconductor regions in a simpler process. -M (Can be applied to JS electrode (wiring) formation, etc.

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 to 3 are cross-sectional views of a semiconductor device in order of steps showing an embodiment of the present invention. 1...N-type substrate, 2...Field oxide film, 3.4...P-type source and drain region, 5...P-well, 6.7...N-type source and drain region, 9...Polysilicon gate electrode, 11...MoSi, l! ,
12...Aluminum layer. Patent Applicant Fujitsu Co., Ltd. Patent Application Agent Patent Attorney Akira Aoki Patent Attorney Kazuyuki Nishidate 1) Yukio Patent Attorney Akira Yamaguchi

Claims (1)

[Claims] In order to form an ohmic electrode contact to both the p-conductivity type semiconductor region and the n-conductivity type semiconductor region using a barrier layer made of high-melting point silicide, a contact layer is formed on the p-conductivity type semiconductor region and the n-conductivity type semiconductor region. A high melting point metal silicide layer is deposited on the high melting point metal silicide layer, and p conductivity type impurities are passed through the high melting point metal silicide layer to form the p conductivity type semiconductor region and the n conductivity type impurity.
implanting ions into a conductive type semiconductor region and annealing the conductive type semiconductor region; When selectively introducing an n-conductivity type impurity into a region where a region is to be formed, an extra amount of the n-conductivity type impurity is introduced by a predetermined amount corresponding to the ion implantation amount of the p-conductivity type impurity. A method for manufacturing a featured semiconductor device.