JPS60180664A - Soldering method - Google Patents
Soldering methodInfo
- Publication number
- JPS60180664A JPS60180664A JP3515784A JP3515784A JPS60180664A JP S60180664 A JPS60180664 A JP S60180664A JP 3515784 A JP3515784 A JP 3515784A JP 3515784 A JP3515784 A JP 3515784A JP S60180664 A JPS60180664 A JP S60180664A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- solder
- semiconductor element
- jig
- soldering
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K13/00—Apparatus or processes specially adapted for manufacturing or adjusting assemblages of electric components
- H05K13/04—Mounting of components, e.g. of leadless components
- H05K13/046—Surface mounting
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K3/00—Tools, devices, or special appurtenances for soldering, e.g. brazing, or unsoldering, not specially adapted for particular methods
- B23K3/06—Solder feeding devices; Solder melting pans
- B23K3/0646—Solder baths
- B23K3/0669—Solder baths with dipping means
- B23K3/0684—Solder baths with dipping means with means for oscillating the workpiece
Landscapes
- Engineering & Computer Science (AREA)
- Mechanical Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Molten Solder (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Die Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
[発明の技術分野]
本発明は半田付は方法に係り、特に基板と半導体素f−
どの半田付けをリフロー炉内で確実に行うためのこの種
方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a soldering method, and particularly relates to a method for soldering a substrate and a semiconductor element.
The present invention relates to a method of this kind for reliably performing soldering in a reflow oven.
[発明の技術的背M]
従来から、基板上に半導体素子を固定する場合は半田付
けによって行われる。半田付けは、まず。[Technical background of the invention M] Conventionally, a semiconductor element is fixed on a substrate by soldering. Soldering first.
半導体素子を基板に位置決めするための治具にセットし
、半田付けされる基板の所定位置に該治具を載せ、基板
上に半田を介して半導体素子を載置する。この基板をリ
フロー炉内で搬送させ、リフローゾーン(加熱領域)で
加熱し、半導体素子と基板との間の半田を溶解すること
によって半田付けに行っている。The semiconductor element is set on a jig for positioning the semiconductor element on the substrate, the jig is placed on a predetermined position of the substrate to be soldered, and the semiconductor element is placed on the substrate via the solder. This substrate is transported in a reflow oven and heated in a reflow zone (heating area) to melt the solder between the semiconductor element and the substrate, thereby performing soldering.
[背景技術の問題点]
しかしながら、従来の方法では単に基板を加熱して半田
を溶かしているため、半導体素子と基板における半IJ
(の濡れ性が悪く充分なじまないという難点があり、ま
た半導体素子と基板との間の半H1層にむらが生じ易い
という難点がある。[Problems with the background technology] However, in the conventional method, the solder is simply heated by simply heating the substrate, so that semi-IJ between the semiconductor element and the substrate is
(There is a problem that the wettability of the material is poor and it does not mix well well, and there is also a problem that unevenness tends to occur in the half H1 layer between the semiconductor element and the substrate.
[発明の目的] 本発明は上記従来の難点に鑑みなされたもので。[Purpose of the invention] The present invention was made in view of the above-mentioned conventional difficulties.
リフロー炉内を搬送させて半田イ4けを行う際に。When transporting through the reflow oven and performing soldering.
治具、基板、半導体素子又は案内板の何れかを振動させ
ることにより、半田付は箇所に振動を与え、半田の濡れ
性を良くし、半田層のむらを除去する半田付は方法を提
供せんとするものである。By vibrating either the jig, the board, the semiconductor element, or the guide plate, we provide a soldering method that vibrates the soldering area, improves the wettability of the solder, and removes unevenness in the solder layer. It is something to do.
[Ji!明の概要]
このような目的を達成するために本発明による半田付は
方法は、リフロー炉内を搬送させて、基板上に半導体索
tを半H1付けするにあたり、該半導体素子を前記基板
に位置決めするための冶具にセットして該半導体素子を
該基板に半LLIを介して載置させ、註基板を前記リフ
ロー炉上に設置された案内板に冶って搬送させると共に
、前記治具、基板、半導体素子又は案内板の何れかを振
動させるものである。[Ji! In order to achieve the above object, the soldering method according to the present invention involves transferring the semiconductor element to the substrate when transporting it in a reflow oven and attaching the semiconductor wire t to the substrate in half H1. The semiconductor element is set on a jig for positioning and placed on the substrate via a semi-LLI, and the substrate is set on a guide plate installed on the reflow oven and transported, and the jig, This vibrates either the substrate, the semiconductor element, or the guide plate.
し発明の実施例]
以1:、本発明の々rましい実/Ii!1例を図面によ
り説明する。Embodiments of the invention] Part 1: Surprising results of the invention/Ii! An example will be explained with reference to the drawings.
即ち、本発明の半田付は方法は、図面に示すような半H
J (Jけ装置により実現される。図面において、リフ
ロー炉l内には順送ベルト2が設けられ−rおり、リフ
ロー炉1のリフローゾーン(加熱領域)付近の上方には
案内板3a、3bが固定設置され、案内板3aは発振器
4が接続されている。That is, the soldering method of the present invention is a half-H soldering method as shown in the drawings.
In the drawing, a progressive belt 2 is provided in the reflow oven 1, and guide plates 3a, 3b are installed above near the reflow zone (heating area) of the reflow oven 1. is fixedly installed, and an oscillator 4 is connected to the guide plate 3a.
そして、搬送ベル1−2上では、冶具5により半田6を
介して半導体素子7を載置した基板8が搬送Jれる。Then, the substrate 8 on which the semiconductor element 7 is mounted is conveyed by the jig 5 via the solder 6 on the conveyor bell 1-2.
このような構成による半田付は装置における半IL1(
=Jけ方法は、まず、半導体索子7が冶具5にセントさ
れる。治具5は半導体素子7の基板8における載置位置
を定めるためのものであり、その基板8上の位置には予
め半田6が置かれる。そして、冶具5にセットさ4した
半導体索子7が定位置に載置された基板8は、リフロー
炉]内の搬送ベルト2上に置かオし、搬送される。該基
板8がリフロー炉1のリフローゾーンのイ1近まで搬送
さ]しると、案内板3a、3bによりガ、ヂトされる。Soldering with such a configuration can be performed at half IL1 (
In the method, first, the semiconductor cord 7 is placed in the jig 5. The jig 5 is for determining the placement position of the semiconductor element 7 on the substrate 8, and the solder 6 is placed in advance at the position on the substrate 8. Then, the substrate 8 on which the semiconductor cables 7 set in the jig 5 are placed in a fixed position is placed on the conveyor belt 2 in a reflow oven and conveyed. When the substrate 8 is conveyed to near A1 of the reflow zone of the reflow oven 1, it is moved by the guide plates 3a and 3b.
このときに発振器4を動作させて案内板3aを振動させ
て該基板8全体を振動させる。リフローゾーンの位置で
は基板8に加熱し半田を溶解して半田イリけを行うが、
このどき案内板3aの振動で半H444け箇所が振動さ
、Iシることにより、半導体素子7の基板8上における
接触面全体に溶解した半田をいき亘らせるようにするも
のである。したがって、半田のrmlシ性が良くなり、
半田層にむらを生ずることもなく半1+j (jけをル
ス「実にすることができる。At this time, the oscillator 4 is operated to vibrate the guide plate 3a, thereby vibrating the entire board 8. At the reflow zone position, the board 8 is heated to melt the solder and remove the solder.
At this time, the vibration of the guide plate 3a vibrates and shakes the half-H444 portions, thereby causing the melted solder to spread over the entire contact surface on the substrate 8 of the semiconductor element 7. Therefore, the RML resistance of the solder is improved,
It is possible to make half 1+j without causing unevenness in the solder layer.
なお、上記実施例では、案内板3aのみを振動させた場
合を示したが、案内板3a、3bを共に振動させてもよ
く、また案内板に限らず1例えば搬送手段等により、冶
具5・半導体索子7・基板8の何JLかに振動を加えて
も同様の効果が得られる。In the above embodiment, only the guide plate 3a is vibrated, but both the guide plates 3a and 3b may be vibrated. A similar effect can be obtained by applying vibration to some JL of the semiconductor cable 7 and the substrate 8.
Claims (1)
(1付けするにあたり、該半導体素Pを前記基板に位置
決めするための治具にセットして該半導体素子を該基板
に半taを介して載はさせ、該基板を前記リフロー炉上
に設置さJした案内板に沿って搬送させると共に、Ou
記治具、基板、半導体素子又は案内板の何4しかを振動
させることを特徴とする半11付は方法。The semiconductor device is transferred in a reflow oven, and half of the semiconductor device is placed on the substrate.
(For bonding, the semiconductor element P is set on a jig for positioning it on the substrate, the semiconductor element is placed on the substrate via a semi-ta, and the substrate is placed on the reflow oven. While transporting along the guide board, Ou
A half-mounted method characterized by vibrating any one of a recording jig, a substrate, a semiconductor element, or a guide plate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3515784A JPS60180664A (en) | 1984-02-28 | 1984-02-28 | Soldering method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3515784A JPS60180664A (en) | 1984-02-28 | 1984-02-28 | Soldering method |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS60180664A true JPS60180664A (en) | 1985-09-14 |
Family
ID=12434046
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3515784A Pending JPS60180664A (en) | 1984-02-28 | 1984-02-28 | Soldering method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60180664A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1989001283A1 (en) * | 1987-08-04 | 1989-02-09 | Western Digital Corporation | Apparatus and method for aligning surface mountable electronic components on printed circuit board pads |
US7367486B2 (en) * | 2004-09-30 | 2008-05-06 | Agere Systems, Inc. | System and method for forming solder joints |
-
1984
- 1984-02-28 JP JP3515784A patent/JPS60180664A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1989001283A1 (en) * | 1987-08-04 | 1989-02-09 | Western Digital Corporation | Apparatus and method for aligning surface mountable electronic components on printed circuit board pads |
US4831724A (en) * | 1987-08-04 | 1989-05-23 | Western Digital Corporation | Apparatus and method for aligning surface mountable electronic components on printed circuit board pads |
US7367486B2 (en) * | 2004-09-30 | 2008-05-06 | Agere Systems, Inc. | System and method for forming solder joints |
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