JPS60176280A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce parasitic resistance by forming a high-conductivity crystal layer on the surface of an operating layer, implanting the same conduction type impurity ions from the surface of the crystal layer so as to pass through the interface between the high-conductivity layer and the operating layer of a substrate in quantity more than a specific quantity and thermally treating the ions. CONSTITUTION:Si ions are implanted selectively to a GaAs substrate 21 to form an operating layer region 22. A resist is removed, and a TiW film is applied and removed selectively to shape a gate electrode 23. An SiO2 film is formed on the whole surface, the surface of GaAs is exposed through anisotropic etching, and side walls 24 consisting of the SiO2 film are left at the ends of the gate electrode 23. A GaAs film 25 is grown on the whole surface, and Si is doped. Si ions are implanted to the whole surface, and stepped sections in a resist film are smoothed. The resist on the gate electrode, the GaAs film and the resist left on a wafer are removed, and an SiO2 film 27 is applied as an inter-layer film. The whole is thermally treated, and the SiO2 film and the resist are removed selectively and a Ti-Pt-Au film is shaped on the whole surface, and source and drain electrode wirings 28 are formed through patterning.

Description

[Detailed Description of the Invention] [Description of the Technical Field to Which the Invention Pertains] The present invention relates to a method for manufacturing a compound semiconductor field effect transistor in which a crystal layer serving as a high conductivity source/drain layer is formed in proximity to a gate region. It is.

[Description of prior art]

Compound semiconductors, particularly gallium arsenide (G (Li2)), are called post-silicon materials, and are currently being researched and manufactured in various places because they are capable of manufacturing field-effect transistors (FETs) and integrated circuits that can operate at high speeds. It has been done.F
Due to the desire to improve the performance of ET characteristics, a manufacturing method is currently known in which a highly conductive source/drain layer (hereinafter referred to as ?l+ layer) is formed in the vicinity of the gate region. Figure 1 shows a schematic cross-sectional view of these FETs.The high-conductivity source/drain layers are made using ion implantation to implant impurities that have the same conductivity type as the active layer, using the gate electrode as a mask. In Fig. 1, 1 is a semi-insulating substrate, 2 is an active layer, and 3 is a semi-insulating substrate.
4 is a gate electrode, 4 is a high conductivity source/drain layer, 5 is an interlayer insulating film, and 6 is a source/drain electrode wiring. In an FET having such a highly conductive source/drain layer, it is possible to reduce parasitic resistance and increase mutual conductance, which leads to improved FET characteristics and integrated circuit performance. As shown in FIG. 1, when a high conductivity source/drain layer, that is, an fL+ layer, is formed by ion implantation, the depth of the n+ layer should be large. It is preferable that the resistance of the ++ layer is small, but -11
As the layer depth increases, the so-called short channel effect becomes more prominent, and as the gate length decreases, the threshold voltage shifts in the negative direction, making it difficult to control the threshold voltage. A problem arises. Shortening the channel is essential for improving FET characteristics, but the shorter the channel, the more necessary it is to reduce the parasitic resistance, and the method of forming one layer by ion implantation can reduce the parasitic resistance and shorten the channel effect. It is currently extremely difficult to achieve both reductions. As one solution to the above problems, the first layer is
A method of providing a crystal layer on the substrate surface that will become the drain region is being considered. FIG. 2 shows a schematic cross-sectional view of such a transistor, where 11 is a semi-insulating substrate, 12 is a semi-insulating substrate, and 12 is a semi-insulating substrate.
is an operating layer, 13 is a gate electrode, 14 is an interlayer insulating film, 15
The cancer layer 16 is source/drain electrode wiring.

Fig. 2 shows an example in which the n1 crystal layer is provided on the surface of the active layer, but after the active layer is slightly scratched by etching? It is also possible to provide a crystal layer. like this? In the method of providing a crystal layer, by keeping the etching depth shallower than the depth of the active layer, the short channel effect can be reduced, and at the same time, the series resistance can be reduced, making it possible to manufacture small to high performance FETs. Considering this, it can become an important manufacturing method.

Several crystal growth methods are well known for forming this n-crystal layer, but the characteristics of the n-crystal layer are greatly influenced by the treatment conditions of the crystal surface where growth begins, and currently no satisfactory results have been achieved. It has not been done.

In other words, the formation of this n-crystal layer is carried out during FET manufacturing, but in this case, the crystal growth starting surface is subjected to various treatments essential for FET manufacturing, and in reality, the n-crystal layer is Does not exhibit the same properties as when formed on untreated crystal faces? Parasitic resistance has not been satisfactorily reduced in transistors manufactured by forming crystal layers. In order to reduce the number of various processing steps before forming the n-crystal layer, some methods are being considered in which the n-crystal layer is formed on the active layer in the early stage of FET manufacturing. Before the formation of the operating layer,
That is, the impurity implantation for forming the active layer and its electrical activation have already been performed, and the same problem as described above may occur.

As mentioned above, on the source/drain region? Although the advantages of providing a crystal layer are well known, the reality is that a satisfactory reduction in parasitic resistance has not been achieved.

[Detailed description of the invention]

Is it possible for the present invention to sufficiently reduce parasitic resistance in consideration of the above points? The present invention provides a novel method for manufacturing a compound semiconductor field effect transistor that realizes a method for forming a crystal layer.

[Detailed description of the invention]

The present invention relates to the production of a conductor field effect transistor in a compound in which a high conductivity crystal layer having the same conductivity type as the active layer is formed on the region that becomes the source/drain region. After forming a conductivity crystal layer, impurity ions having the same conductivity type as the high conductivity crystal layer are implanted from the surface of the crystal layer. This method of manufacturing a semiconductor device is characterized by performing a process of selecting and implanting ion energy so that the amount of ions passes through the ions, and performing heat treatment.

[Explanation of Examples]

An example will be described below to provide a detailed explanation of the present invention. In FIG. 3 (α), a semi-insulating GaAs substrate 2
1, Si ions were applied at 70KgV using the resist as a mask.
The active layer region 22 is formed by implanting 2XIO"ci with an ion energy of
Using the patterned photoresist as a mask, the TjW film is removed by dry etching to form a gate electrode 23t.

Next, a silicon oxide film with a thickness of 300 OA is formed on the entire surface of the sample, and the silicon oxide film is etched to become source/drain regions using a parallel plate dry etching device and an anisotropic etching method using CF4 gas. The Gaps surface is exposed, and the sidewall 24 of the silicon oxide film is left at the end of the gate electrode 23.

Next, in FIG. 3(b), using the molecular beam crystal growth method,
On the exposed GcLA8 surface, an @A8 film 25 was grown to a thickness of 2000^ over the entire surface to form a single crystal film. that time,
Si was doped so that the electron concentration of the Gaps was lXIQ"m-3. Next, Si ions were
, lX1015CrrL-3, a photoresist 26 was further applied over the entire surface, and the resist was softened by baking at 180° C., so that the step of the resist film covering the gate electrode step was smoothed. In FIG. 3(c), the entire surface is etched using an ion milling device, the resist and GaAs film on the gate electrode are removed, the resist remaining on the wafer is removed, and silicon oxide is used as an interlayer film. A film 27 is deposited to a thickness of 200 OA. Next, heat treatment was performed at 800°C for 20 minutes in H gas, and using the patterned resist as a mask, the silicon oxide film at the source/drain electrode and gate electrode extraction parts was removed, and after the resist was further removed, the entire surface was heated. A 'l'j-pt-Au film is formed on the film and patterned using an ion milling device to form source/drain electrode wiring 28, thereby completing the A++FET shown in the figure.

[Detailed description of the invention]

According to the above, in addition to the GaAsFET produced by the method of the present invention,
For comparison? In addition to transistors using the conventional method without Ar ion implantation and high-temperature annealing (800° Cl2O in H2 gas) after crystal layer growth, S
Although no i-ion implantation was performed, a transistor was manufactured by performing high-temperature annealing.

Gate length 1 μm manufactured by the above three manufacturing methods
, 20 transistors each having a gate width of 10 μm were selected, mutual conductance and source resistance were measured, and their average values were calculated. The results are shown in the table below, and the transistors manufactured by the method of the present invention had a low source resistance and a high mutual conductance value, confirming the effects of the present invention.

In the above embodiments, a high conductivity n-crystal layer was formed immediately after exposing 88 to the source/drain region α.
The effect of the present invention was confirmed by implanting Si ions even in the case where the n-crystal layer was formed after exposing the gap plane and slightly etching it.

In the examples described above, an example using Si ions was shown, but the same effect was confirmed when S+StL+Tg was used instead of Si.

In the above embodiment, after forming the gate electrode and exposing the Gaps surface in the region that will become the source/drain, ? Although the case where a crystal layer is formed has been described, it is clear that the method of the present invention can also be applied to a method in which a crystal layer is formed after layer formation and before gate electrode formation.

+ The method of the present invention implants an impurity having the same conductivity type as the n-crystal layer. It is characterized in that it passes through the interface between the crystal layer and the substrate active layer and disturbs the crystallinity of the interface. The lower limit of the amount of ions passing through the interface is determined from the fact that if it is too small, the degree of disturbance of crystallinity at the interface will be small.
It is reasonable to choose XIO”cm-2 or higher.Also,
In principle, there is no upper limit to the amount of ions passing through the interface in the method of the present invention, but if the amount of ions passing through is selected to be large, the implantation time will take longer, which is not a good idea.

Although the above description is about the case where GcLA8 is used, it is clear that the present invention can also be applied to field effect transistors using other compound semiconductors.

[Brief explanation of drawings]

Figure 1 is a schematic cross-sectional view of a conventionally well-known field effect transistor in which a high conductivity source/drain layer is formed by ion implantation, and Figure 2 is a schematic cross-sectional view of a field effect transistor in which a high conductivity crystal layer is formed on the source/drain region. FIGS. 3(α) to 3(c) are schematic cross-sectional views of a conventionally well-known field effect transistor. FIGS. 3(a) to 3(c) are schematic cross-sectional views showing an example of the manufacturing process of a field effect transistor using the method of the present invention. 21... Semi-insulating substrate, 22... Operating layer, 23...
・Gate electrode, 24... Silicon oxide film sidewall formed at the end of the gate electrode, 25... Highly conductive crystal layer, 2G...
Resist, 27... Interlayer insulating film, 28... Source.
Drain electrode wiring patent applicant: NEC Corporation Figure 1 Figure 2

Claims (1)

[Claims] (1) In a method for manufacturing a compound semiconductor field effect transistor, in which a high conductivity crystal layer having the same conductivity type as the active layer is formed on the surface of the active layer that will become the source/drain region. After forming a high conductivity crystal layer, impurity ions having the same conductivity type as the high conductivity crystal layer are implanted from the surface of the crystal layer. 1. A method for manufacturing a semiconductor device, comprising the steps of selecting and implanting ion energy such that an amount of ion energy passes through the semiconductor device, and performing heat treatment.