JPS60176150A - Operation control system of information processing unit - Google Patents

Abstract

PURPOSE:To track easily the operation of a hardware of an optional information processing unit by starting the 2nd means when the logical state where the 1st means is designated in advance is detected. CONSTITUTION:A logical circuit 1 detects the establishment of A.B+C as to three state signals A, B, C. In the MODE1, an AND gate 4 is made effective and a state detection signal 2 is transmitted to a counter 6 via an OR gate 5. When a mode signal MODE1 is zero, an AND gate 3 is made effective. Then a value of a count-up signal X is transmitted to the counter 6 via a gate 5. A logical circuit 7 is made effective by the MODE2 and a clock K1 reaches zero when the signal 2 is set so as to stop the operation of the distributed circuit. In the MODE3, an AND gate 8 is made effective and when the signal 2 is set, the present content of the register 10 is stored. In the MODE4, the AND gate 11 is made effective, and when the signal 2 is set, the content of the history circuit 13, that is, the value of a signal group S1 is stored.

Description

[Detailed description of the invention]

[Technical Field of the Invention] The present invention relates to an operation control method for testing or diagnosing an information processing device such as a computer, and in particular, when the operating state of the device satisfies a pre-specified logical condition, clock stoppage, freeze, etc. This invention relates to a control method for tracking the motion of a person. [Technical background] Traditionally, logic testing of the hardware of information processing equipment. When investigating problems, etc., the method used is to run a program to see the actual operation of the hardware, and various functions have been considered as tools for this purpose. For example, each clock is given by a human pushing a button by hand. The computer status and device status, that is, the contents of various control latches and registers, are sent to 5 CAN OU every clock.
This is the function that can be seen by T, etc. However, performing this operation on hundreds or thousands of clocks was a heavy burden on nine workers. In addition, in recent years, control has become more complex as some machines, such as scientific and technological computers, operate multiple machine language instructions in parallel or overtake each other. In such computers, it is extremely difficult to track hardware operations, and new tools are required. [Object and Structure of the Invention] An object of the present invention is to provide an operation control method that enables easy tracking of the operation of hardware of any information processing device. Therefore, the present invention activates various functions for tracking the operation of a computer when a desired logic state determined by one or more logic signals is established during the operation of the information processing device, and the configuration thereof is as follows. a first means for detecting that a pre-specified logical state is established in the information processing apparatus; a second means for controlling the operation of the information processing device;
and third means for activating the second means when the means detects that a predetermined logical state is established. [Embodiments of the Invention] Details of the present invention will be described below based on Examples. FIG. 1 is a block diagram of a circuit according to one embodiment. In this embodiment, a state detection signal 2 outputted by a logic circuit 1 that detects establishment of a desired logic state, and MODE1 to MODE4 shown below are used.
In combination with a mode signal specifying a tracking operation mode, the tracking operation of the specified mode is activated. - MODEI: Counts the number of times a desired logic state is established. ■MODE2: Stop the clock. ■ MODE3: Record the status at that time ■ MOD
E4: Records from the current state to the state several cycles ago. The logic circuit 1 detects that the following equation holds true for the three status signals A, B, and C. A-B+C・・・・・・・・・・・・ [Formula l] MOD
In EL, AND gate 4 is enabled. The state detection signal 2 is transmitted to the counter 6 via the OR gate 5. The counter 6 counts up the number of times the state detection signal 2 is turned on from off. Mode signal M
i if ODEI is II OII. The output of the AND gate 4 becomes II O11, which instead enables the AND gate 3 having an inverter at its input. Therefore, the value of the count-up signal X is transmitted to the input of the counter 6 via an AND gate 3 and an OR gate 5. This is a state in which the counter 6 is used for a purpose other than the purpose of the present invention, and the counter 6 is counted and amplified by the signal X. This switching is performed by the mode signal MODE1. In MODE2, when the logic circuit 7 is enabled and the state detection signal 2 is turned on, the clock CLOCK1 becomes II O
11, and the operation of the circuit to which CLOCR is distributed can be stopped. However, distribution of CLOCKO will continue. In MODE3, AND gate 8 is enabled. When state detection signal 2 turns on, the CLOCK 5TOP signal applied to register IO turns on, and the current contents of register IO, S0, are held. In other words, the values of the plurality of signal groups S0 at the time when the condition of [Formula 1] is satisfied are held. Here, register 10 retains its value S once the CLOCK 5TOP signal is turned on - until it is reset thereafter. It is designed to hold. Note that the OR gate 9 is provided to perform the same function even when an error occurs. In MODE 4, when AND gate 11 is enabled and state detection signal 2 is turned on, FREEZE HISTO
The RY signal turns on, and the contents of the history circuit 13 Sl+
That is, the value of signal group S+ is held. The history circuit 13 has a memory structure with addresses, and the write address cyclically repeats the values from θ to N-1, and writes a new signal group S every cycle. When the FREEZE HISTORY signal turns on, the SI from S at that time to N-1 cycles before, that is, N
The value of S for cycles can be recorded as a history. The history circuit 13 is. When the FREEZE HISTORY signal turns on, it freezes at that point and RESETHI 5TO
The history of the value S1 is held until the RY signal is turned on. Note that the OR gate 12 is provided to perform a freeze function when an error occurs. In the embodiment described above, the state detection signal 2 that activates the control circuit of each mode of MODE to MODE 4 is turned on when the logic state of [Formula 1] is established in the logic circuit 1, but [Formula 1] ] It may be necessary to investigate the relationship between the number of times the equation is satisfied and the occurrence of an error. In this case, [Formula 1
] It would be convenient if the state detection signal 2 could be turned on when the condition . FIG. 2 shows an embodiment circuit having means for activating the tracking function when the number of times a desired logic state is established reaches a predetermined number. In the figure, 1 to 6 represent elements with the same numbers in FIG. Further, 14 is a counter output signal, and 15 is a comparison circuit. 16 is a register for specifying the number of times, and 17 is a coincidence output signal. The counter 6 is counted and amplified every time the logic state of [Formula 1] is established, and a count output signal 14 representing the count value is inputted to the comparator circuit 15. Here, it is compared with the number of times of establishment set in advance in the register 16 for specifying the number of times. When the comparison circuit 15 detects a match, the match output signal 17
is turned on as a control signal to activate each tracking function as shown in FIG. It is used in place of the state detection signal 2. Note that since the counter 6 is used for another purpose using the count-up signal X, it is also possible to provide an independent counter for the number of times the logic state is established in this embodiment. By the way, in the embodiment circuit shown in FIG. 1, the logic state is taken regarding the combination of the values of a plurality of signals. However, it is also possible to set a logic state with respect to a change in the value of one or more signals. FIG. 3 shows another embodiment of the circuit including a logic circuit for detecting changes in this unusual signal. The Kono circuit uses the 5CAN 0tJT function to read out the data set in the latch specified using the 5CAN ADDRESS function, compares this with the data input using the 5CAN IN function, and if they match, outputs the clock. It works to stop. In the figure, 18 is a latch (0), 19 is a latch [l], 20 and 21 are EXCLUSIVE NOR games),
22 and 23 are AND gates, 24 is an OR gate, 2
5 is an AND gate, Die and Dl are latches

[0]
and input data to [1]. DO, # and DO+ are lasso f (0) and [1]
Output data from , 31 is 5CAN IN signal. SO is 5CAN OUT signal, sA is S CANADD
RESS, C3 represents the CLOCK 5TOP signal. First, output data DO0 will be explained. Latch (0)
In, when SAo becomes FT 1 #l, SO. The O value will be equal to DOo. EXCLUSI VEN
The OR gate 20 checks whether SOo is on or off. The designation of whether the comparison target is on or off is given by SI. In other words, the output of the gate 20 is turned on only when SOo matches Sl, and the launch [0
] is addressed, AND gate 22 and O
7. Through the R gate 24. CLOCK 5TOP signal cS
;Ii-"l" ni. In other words, Sl, = “0” (7)
When 500 is off, game) 20 and 22
The output of C8 becomes "IIT" and the output of C8 becomes "III". On the other hand, when 5I=yt 1", cs becomes ff l II when SOo is turned on. The same operation as above is performed for DOl. Here, SAo - "'1", SAt = "
O'', in this circuit, the value of C8 is determined only by ON/OFF of DOo.SA, = ``O'', SA, = 1
# When it is I It, the value of C8 is determined only by DOl. Also, when S A o = S A I = “1”, Doo. The value of C3 is determined by whether one of DOl is turned on or off. Furthermore, if the OR gate 24 is made into an AND gate. The dSO value can be determined by both DOo and DOl being turned on or off. C8 is sent to the tack distribution circuit. Here, in the AND gate 25, the signal CLOCK 5TOP MODE
CLOCK, IT by CS when is If I IT
It can be OII. As a result, CLOCR,
can stop the operation of the circuit to which it is distributed. However, CLOCK++ is distributed to circuits that do not want to be stopped. Note that the signal CLOCK 5TOP MODE is
This corresponds to the mode signal MODE2 in the embodiment of FIG. Regarding the C8 signal, as in the case of the embodiment shown in FIG.
It can be applied to gate 25. In this case, the counter 6, comparison circuit 15 . Number of times specification register 1
The mechanism in No. 6 can be applied as is. By providing a clock stop function using this counter, when an error occurs and the device is stopped, if you check the counter value using 5CAN OUT, etc., you can see how many times C8 was turned on or when the error occurred. I understand. After that, if you set a value smaller than this number in the number specification register, stop the clock once there, and then turn on the clock manually, for example, one clock at a time, you can quickly get the clock near the timing at which the error occurred. Status can be tracked. The above embodiments do not limit the scope of application of the present invention; for example, any desired logic state may be used. Alternatively, a plurality of circuits for detecting logic states may be provided and a desired logic state may be selected by MODE. Furthermore, any suitable function can be used as a function for tracking the movement as required. [Effects of the Invention] According to the present invention, even when an information processing device performs complicated operations, it is possible to effectively use a function for tracing various operations by going into detailed logical states of the hardware. In addition, in the method using a counter, it is possible to know how many times a desired logic state has been established when an error has occurred, so by setting a value smaller than this number of times, it is possible to track the operation shortly before an error occurs. various functions can be enabled. These tools make it much easier to perform logic tests, fault investigations, etc. of information processing equipment than before.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of one embodiment of the present invention, FIG. 2 is a circuit diagram of another embodiment in which a part of the embodiment circuit of FIG. 1 is modified, and FIG.
The figure is a circuit diagram of yet another embodiment. In the figure, 1 is a logic circuit, 6 is a counter, 10 is a register,
13 is a history circuit, and 15 is a comparison circuit. 16 is a register, 18 is a latch (0), Dl is input data, and Do. is the output data, Sl is the 5cAN IN signal, so. is the 5CAN OUT signal. SA, is 5CAN ADDRESS signal, CS is CLO
Represents the CK 5TOP signal. Patent applicant Fujitsu Ltd. Representative Patent Attorney Fumihiro Hase (1 other person) Figure 2 #3

Claims (1)

[Scope of Claims] (11) In the information processing device, a first means for detecting that a prespecified logical state is established; a second means for controlling the operation of the information processing device;
and third means for activating the second means when the means detects that a predetermined logical state is established. (2) first means for detecting that a pre-specified logical state is established in the information processing device; a second means for controlling the operation of the information processing device;
and third means for counting the number of times the means detects that a predetermined logical state is established, and activating the second means when the count value reaches a predetermined value. An operation control method for an information processing device, characterized in that: