JPS58115516A - Bus tracer - Google Patents

Abstract

PURPOSE:To leave a program step, which is the cause of an error, in a tracer, by designating an address range where a program to be debugged is stored and tracing addresses and data in this range. CONSTITUTION:A bus tracer BT is connected to a bus, and data and an address are set to a data register DR and an address register AR respectively in every cycle. The upper limit address and the lower limit address of the address range are set to registers UAR and LAR respectively. Exclusive NORs ENOR between corresponding bits of register AR and UAR and between respective bits of registers UAR and LAR are operated by gates EG, and ANDs between these results and adjacent bits are operated in order from the upper digit side, and OR and AND between results of NOT I of these ANDs and ENOR between AR and UAR are operated, and an address pertinent signal HIT is obtained. AND between outputs of registers DR and AR and the signal HIT is operated by a gate AF' and is inputted to a push-down memory PM. An address counter ACT of the memory PM is counted up by the signal HIT, and thus, faults for debugging of software are inspected.

Description

[Detailed description of the invention] [Technical field of the invention]

The present invention particularly relates to a bus tracer that is connected to a bus between a processing device and a memory in an information processing system and the like, and is used to trace data flowing on a path to diagnose a failure.

[Prior art and problems of the invention]

Although such bus tracers have existed for a long time,
The conventional type traces the data on the path, and even when used in combination with a diagnostic device, etc., it is often controlled to operate in the special electric mode, so that it is not in operation. In this case, all data sessions were traced. The tracer's memory capacity is naturally limited, and therefore push and down memory is generally used cyclically. Therefore, only the past N cycles (the capacity of the NU pushdown memory) remain in the memory. On the other hand, the majority of failures in information processing systems are caused by program malfunctions due to programming errors. Specifically, programs jump to addresses that are not supposed to be accessed, resulting in an infinite loop. Sometimes I do tO. In such a case, if the number of cycles from the execution of the above-mentioned program until a detectable error occurs and the processing is stopped is greater than N, then Information may not remain in the tracer.

[Purpose of the invention]

The present invention prevents the erroneous program step that is the cause from remaining in the tracer even in the above case.
For this purpose, the address range ktIi where the program to be debugged is stored is added, and only when an access to an address within that range occurs, that address and data connection are traced. If you do so, the access will jump outside the above range when executing the program step and the user will not be able to access the program.
! Even when loop 1 occurs, only the addresses within the range are traced many times, so the trace contents can be traced many times. [Embodiment of the Invention] The figure is a block diagram of an embodiment of the present invention.
T is connected to bus BUBK, and data is sent to data register DR.
The K and It addresses are respectively set in the address register AR every cycle, and the upper and lower limit addresses of the 60 address range are set in the registers UAR and LAR, respectively. In addition, as described later, the upper and lower limit addresses tl! OAR,L
You can set it to either AR. Each bit of AR is exclusive-ORed with each corresponding bit of AR. Furthermore, the INOR result of UAR and LAR is ANDed (AN) with adjacent bits from the upper digit side.
D) is taken sequentially by \AND game)AG. OAR and L
AR12) The output of the enemy high-order bit of the NOR result and the output of each of the above MND game) AG are added (!) to the above AR and U A RI) The NOR result and the logical sum (OR) are added.
The output of each OG is ANDed by a multi-input AND gate ANDG to obtain an address signal (11T). On the other hand, the output of DR and the output of AH are gated with a HIT signal by a large number of AND gates AG'. t7t push, down memory PM address counter A
CT is also advanced by HIT1M. The operation of the above circuit will become clear with reference to the following table. The following table FiUA11c"01100101"' i.e. 16dl
1 display Te (65Il@t 7j L h RIC'''0
1111011'', that is, 16-way display (7B) 1g1z set (■, ■). Therefore, OAR and LAR
, the ENOR output becomes "1txoooot1" (
■). From the high-order side of the ■ column with
If we take DQ, we get jllll, and if we take the result and 114-bit sum NDQ, we get "0," and then we take AND'i in order (■) 0. The negation of the most significant bit in the ■ column and each bit in the ■ column is "00011111. “It becomes (■). Next, the address power on the ARIC set vomit friend bus” 01
110101” Soku'S) 16 road display (75) III+
(If you use l+, ENORlt between AR and UAR
The output is "11101111'" (■) 0 If we ORk this with the previous I output (■), we get "1111111"
Becomes bi (■). Therefore, the output of ANPG is “1” and 0
EiIT signal is output. The meaning of the above operations will be explained. ■～■ke, UAR
This step is to search for pit 1 that matches from the upper side of LAR. ■ is tiA for the matching part
The ENOR result of R and UAR is used, but it corresponds to mask information for forcibly setting i to "1" for anything below that value. That is, this embodiment extracts a common bit part from the upper side of UAR and LAR, compares only that part with the corresponding part of AR, and if the part matches, it is considered to be within a predetermined range. ◎ Therefore, in the above example, to UAR (+55111.LAR to (7Blxs
2 sectors and t are actually traced (6G)1
g to (7F)16. Therefore, even if the lower limit address is placed in the UAR and the upper limit address is placed in the LAR, the result will be four times the same. Although it is not possible to specify a range with 7t@kana n degrees, it is possible to trace a slightly wider range of t that includes that range, so in practice there is no interval at all.

【Effect of the invention】

As described above, in the present invention, since only the data within the address range of the special telephone is traced, software debugging and path failure investigation can be effectively performed even with limited RT push and down memory storage. The comparison method for the te address range can also be done using only the ENOH of the upper bits as described above, so the commonly considered methods,
For example, the difference between AR and UAR and the difference between AR and LAR,
Compared to the method of checking whether the results are within the range based on the sign of the results, faster comparison can be performed using less hardware.

[Brief explanation of the drawing]

The figure is a block diagram of an embodiment of the present invention, where DR is a data register, R is an address register, UAR, and LARH.
Upper/lower limit address register, PM is push, down memory, ACTF'i address counter, KG is ENOR gate, AG, muG', ANDG is AND gate, och
OR gate, ■ is an inverter.

Claims (1)

[Claims] In a bus tracer that is connected to an address bus and a data bus and that sequentially stores addresses and data on the bus in pairs in a book and a down memory, a means for specifying an upper limit address and a lower limit address, and a means for specifying an upper limit address and a lower limit address; Push the above address and data only when the above address is within the range of the upper limit address and lower limit address.
A bus tracer having means for storing in down memory.