JPS60173948A - Jitter canceller - Google Patents

Abstract

PURPOSE:To improve the jitter suppressing capability by correcting sequentially a forecast coefficient so that an identification error power to a complex base band signal after phase correction is decreased. CONSTITUTION:When a momentary position signal 102 is inputted to a register 103, each content is outputted from each stage, and integrated to an accumulator 108 while being weighted. Since an output of the accumulator 108 indicates a forecast value of an instantaneous phase, a complex triangle function generator 109 outputs a complex signal, is multiplied with the complex signal from an input terminal 101 at a phase rotating device 104 and the result is fed to an identifier section 106, which identifies the received data and transmits an identified error signal, a phase correction error signal is detected and fed back to correlation detectors 121-123 so as to correct the forecast coefficient in the direction that the correlation is decreased. Thus, no phase noise is included in the complex signal inputted to the identification section 106 and data identification with less error is conducted stably.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a data transmission system that transmits data using an analog line such as a telephone line, and particularly to a carrier phase control system in a receiving section thereof.

(Prior Art and its Problems) Generally, in a data transmission system, lines are subject to various signal deteriorations such as multi-amplitude distortion, delay distortion, carrier frequency offset, and carrier phase jitter. Among these, amplitude distortion and delay distortion are almost time-invariant, or even if they are time-varying, they only change slowly.
These distortions can be compensated for by so-called automatic equalizers. On the other hand, carrier frequency offset and carrier phase jitter cause time-varying distortion, and in order to absorb this, conventionally, a feed control system such as a phase-locked loop has been used. In particular, the carrier phase shift occurs in a carrier wave supply device or the like in an analog transmission link and has a periodic component near the AC cycle 501]z or 6011z of the commercial power supply. Thus, for example, the so-called baud rate, which corresponds to the clock speed of the data transmission system, is 2400
It is about 11z.

In order to absorb the jitter of 6011z, it is necessary to make the equivalent quality factor of the phase-locked loop 40 or less, which deteriorates the Gaussian noise suppression ability of the phase-locked loop. Usually, the loop band of such a phase-locked loop is adjusted to achieve a trade-off between jitter suppression ability and Gaussian noise suppression ability. In other words, the noise suppression ability of the phase-locked loop is sacrificed in order to provide the carrier phase jitter suppression ability.

(Objective of the Invention) An object of the present invention is to provide a jitter canceller with a wide variety of jitter suppression capabilities without sacrificing the noise suppression capability of a conventional phase-locked loop.

(Structure of the Invention) According to the present invention, there is provided an N-stage register into which the outputs of the instantaneous phase detection means and the shadow instantaneous phase detection means are sequentially input, and the output of each stage of the register is multiplied by a prediction coefficient. a predictor that generates a phase predicted value by adding all of these together;
a phase rotator that corrects a phase shift of the complex baseband signal according to the phase prediction value, and successively corrects the prediction coefficient in order to reduce identification error power for the complex baseband signal after phase correction. A characteristic jitter canceller can be obtained.

(Principle of the invention) As already mentioned, in the conventional phase-locked loop,
Carrier phase jitter suppression capability was provided at the expense of noise suppression capability.

However, considering that carrier phase jitter, which causes signal deterioration, has strong periodicity as described above,
If it is possible to predict this periodic jitter in some way, and if the jitter can be removed using this prediction result, the loop band of the first phase-locked loop can be adjusted independently of the jitter frequency. It should be possible to suppress Gaussian noise by making it narrower.

The present invention provides a jitter canceller with high jitter suppression ability based on the above idea, and is based on the principle shown below.

It is now assumed that signal processing in the receiving section of the target data transmission system is performed using a sample value system with a period of T1 seconds, and the theater viewing value of the instantaneous phase at the m-th time is Ym. ym is expressed as the sum of the true phase xm and the noise component nm mixed in the observation system.

yal = Xm '' nm If the estimated phase obtained by linearly weighted addition of the observation series (y,,) is xl, then it is expressed as Δ N-1 XIH-ΣaiYm-i -0. However, jLOnal+...・raN-
1 is a prediction coefficient, N is a prediction order, and as described later, the larger N is, the higher the prediction accuracy of the estimated phase becomes. Furthermore, the difference between the suffixes and m reflects the time difference between the time of phase observation and the time of verifying the correctness of the estimated phase.

Now, the above prediction coefficient a. , al, . . . +aN-1 must be adjusted to obtain as accurate an estimated phase as possible, but in order to do so, the correctness of the above estimated phases must be verified in some way.

Here, if the true phase Xk is known, the estimation error is 2△
! Prediction coefficient a to minimize the average value of the power (xk-xi). , al, . . . , aN-te may be determined. However, if the true phase xk is known, there is no need to estimate Xk, and normally Xy is an unknown quantity. Therefore, it is impossible to use the above (xh-xk) as an evaluation function for determining prediction coefficients. Fortunately, however, the data identification error zk after phase correction using the estimated phase xk is approximately △ Zk = (xk - xk) xC + α, where C is a constant and α contains noise uncorrelated with Xk + Xk. , and in this case, the root mean square value J of zk becomes J=(Xk-Xk) XC+A. However, A is the power at α. Therefore, the prediction coefficient a is set in order to minimize the root mean square value of the sincerity error. .

al,...+aN-t'(+?) is determined, the resulting prediction coefficient will minimize the average value of (xk-xk).

Therefore, the time prediction coefficient a. (')*at(k)
e...

Prediction coefficient a at the (1st (+t)th time) (h+1) for aN-1(k).

If a, (h+x), +·+, aN-1(h+1) are successively corrected using the following equation, a prediction coefficient that minimizes (xl, -Xi) will be obtained. That is, where ε is a correction coefficient and corresponds to the time for which l/ε averages z%. The above formula can be written as history. This modification algorithm is generally known as the steepest descent method, and convergence is guaranteed as long as the correlation matrix Φ defined by the following equation is a positive constant.

However, Ryy(4=y□7m+4) The present invention is basically based on the above principle, and removes the JIR phase by rotating the phase of the received complex baseband signal by the predicted instantaneous phase. The aim is to

Now, let the th sample value of the biplane baseband signal be γ
, and let η be the complex signal obtained by giving a phase rotation of xk to this, then let ηk and γ be @exp(-
+zk) The following relationship holds true. Here, if ηk is a complex signal obtained as a demodulation result of a VSB (residual sideband modulation) signal, its real part carries the desired data, so the identification error zk is zk ” Re (ηb ) dk.However, R6(.) represents an operation to extract only the real part, and dk represents identification data.Therefore, aZ.

−= Re () (' a , (k) a a 1 (k) = Im (ηk
)・3′m−i However, Im(ηk) represents the imaginary part signal of η, so the・IC positive algorithm of the consonant coefficient is 6,(i+
+1) = al(k)-2ε・zk・1m(ηi
)・ym−+ (1) The meaning of the above expression is as follows. That is, the i-th constellation coefficient at the (k11)th time is obtained by multiplying the following correction amount by an appropriate correction coefficient from the i-th consonant coefficient at the (k11)th time: subtracting ii. It is executed by The second time and "th" correction amount is obtained as the product of the discrimination error zk at the -th time and the imaginary part signal at the second time. The ym-1'e multiplication obtained by ゝ, can be obtained by combining.

Next, if ηk is a complex signal obtained as a result of demodulating a normal QAM (@cross amplitude modulation) signal, the prediction coefficient modification algorithm corresponding to equation (1) can be written as follows.

@, (k+t)-aI(k)-26(ZR, ni-1m(
ηJ"Zl, h"a(ηh)) ym-+ (21 However, ZR, ke ZI, k respectively represent the real part identification error and the imaginary part identification error at the time. (1)
(Generalizing Equation 21, @, (k+1) −al(k)−ε0ξk′ )′+
It is summarized in the form of a correction algorithm n-1, and ξ is regarded as a signal corresponding to the phase correction error at the first time.

(Embodiment) FIG. 1 is a block diagram showing a general embodiment of a jitter canceller according to the present invention. In the figure, reference numeral 101 is a first input terminal into which a complex baseband signal is input, and reference numeral 102 is a second input terminal into which an instantaneous phase signal obtained as the output of the phase detection means is input. , reference number 103 is a register into which the instantaneous phase signals are sequentially input. Each stage of the register 103 outputs each content, for example, the first stage output is the first load section 11
1, the second stage output is weighted by the second loading unit 112, the final stage output is weighted by the final stage loading unit 113, and each weighting result is weighted by the accumulator 108. It is accumulated. The output of the Aki △ mulrator 108 indicates the predicted value Xkk of the instantaneous phase9, and the complex trigonometric function generator 109 receives the predicted value △ △
Reference p@signature 104 represents a phase rotator which outputs a complex signal exp(ixl, ) with k as an imaginary part, and a complex trigonometric function generator for the complex signal input from the first input terminal 101. The above exp(-+x
+c) 'li' and supplies the result to the identification unit 106.The identification unit 106 identifies the received data according to the conversion method such as VSB, QAM, etc. It is delivered to the detection unit 107. In the phase correction error detection unit 107, the phase correction error signal ξ is given as 'ft:
This signal is immediately sent to correlation detectors 121 and 122 to calculate the correlation with each stage output of the register 103.
Returned to 23rd. In response to this feedback, for example, the correlation detector 121 detects the amount of correlation between the first stage output of the register 103 and the phase correction error signal, and controls the first load section 111 in a direction that reduces this amount of correlation. Modify the prediction coefficients. Thus, in a steady state, the complex signal input to the identification unit 106 contains almost no phase noise, and data identification with few errors is stably performed.

Various configurations are possible for the correlators 121, 122, 123 shown in FIG. 1, but for example, in the first specific configuration example shown in FIG. multiplier 20
In step 3, these products are taken. This product signal is sent to the adder 2
04. First load section 205° 1 sample delay circuit 206
and is averaged over a sample period. At this time, the integration period is the first load section 205
If the weighting coefficient of is β (however, β<1), then 1/(1-β
). The thus integrated signal is multiplied by an appropriate coefficient in the second loading section 207 and is delivered to the output terminal 208 as a correction signal for the prediction coefficient.

FIG. 3 is a circuit diagram showing a second specific configuration example of the correlator shown in FIG. 1, in which reference numbers 303 and 304 are polarity detectors, and reference number 305 is an exclusive OR the circuit,
Reference number 306 represents a selector.

In the figure, the polarity of the register output and phase error signal input through terminals 301 and 302 is determined, and if both have the same polarity, a logic "1" signal is generated, and if both have different polarities, a logic "θ" signal selector 306
is input to the control end of. The selector 306 selects the positive level 1Δ or the negative level −Δ according to the logic level of the control signal obtained above, and the output is sent to the adder 307. The sample delay circuit 309 is supplied to an integrator consisting of a load section 308.1 and a sample delay circuit 309. The signal thus smoothed by the integrator is outputted to the terminal 310 as a correction signal for the prediction coefficient.

Identification unit 106 and phase correction error detection unit 107 in FIG.
The structure differs depending on the modulation format used.

FIG. 4 is a circuit diagram showing a specific configuration example of the identification section and the phase correction error detection section when VSB is used as the modulation format. In the figure, the real part and imaginary part of a complex baseband signal are input through terminals 401 and 402, respectively. For the real part signal, a discriminator 403 identifies data that is compatible with the real part signal, and a subtracter 404 detects a difference of one. The job-specific error thus obtained is multiplied by the imaginary part signal in a multiplier 405, and a phase correction error signal is outputted to an output terminal 406.

FIG. 5 is a circuit diagram showing a specific configuration example of the identification section and the phase correction error detection section when QAM is used as the modulation format. In the figure, the real part and imaginary part of the multi-line baseband signal are inputted via terminals 501 and 502, respectively, and identifying sections 503 and 504 identify the data carried by each. Subtractors 505 and 506 each represent a real part identification error.

The imaginary part identification error is detected, and the thus detected real part identification error and imaginary part identification error are multiplied by the imaginary number signal and the real part signal in multipliers 507 and 508, respectively.

The multiplication results of the two systems obtained in this manner are added by an adder 509 and a phase correction error signal is outputted to an output terminal 510.

FIG. 6 is a circuit diagram showing a specific configuration example of the identification section and the phase correction error detection section when so-called staggered QAM is used as the modulation format. In the staggered QAM, the real part and the imaginary part of the complex baseband signal inputted to the terminals 601 and 602 alternately carry data one sample at a time. The first selector 603 selects the signal carrying data and supplies the selected signal to the discriminator 605. On the other hand, the second selector 604 selects the signal that does not carry data and supplies the selected signal to the multiplier 607. Subtractor 606 detects the identification error and supplies the result to multiplier 607. Multiplier 607
By multiplying and combining the two input signals, a phase correction error signal is generated and outputted to a terminal 608.

FIG. 7 is a block diagram showing the basic configuration of a data receiving system to which a jitter canceller according to the present invention is applied, in which complex baseband signals input multiple times through a terminal 701 are transmitted to a phase rotator 702 and an instantaneous phase detector 704. The signal is supplied to a phase control loop consisting of a loop configuration of a voltage control oscillator 703 and a voltage control oscillator 703, and phase fluctuations that are sufficiently slow compared to the sample speed are absorbed. The output of this phase control loop is input to a conventional automatic equalizer 705, where the width distortion and delay distortion caused by the transmission line are equalized. Therefore, the output of the automatic equalizer 7θ5 contains only phase noise that changes quickly over time, so-called jitter. This jitter is absorbed by the jitter canceller 706 according to the present invention. Note that the data identification error signal necessary for correcting the tap coefficients of the automatic equalizer 706 is supplied from the jitter canceller 706. Therefore, automatic equalizer 70
The tap coefficient of 6 does not contain fluctuations due to jitter and exhibits its original equalization ability. Also, the instantaneous phase signal to be stored in the register in the jitter canceller is sent to the instantaneous phase detector 7.
Supplied from 04. At this time, a certain amount of delay will be included between the complex baseband signal input to the jitter canceller and the instantaneous phase signal, which should be the data for predicting the jitter contained therein. Considering that the delay is usually dominated by periodic components, the jitter removal characteristics of the jitter canceller will hardly deteriorate even if such a delay exists.

When the jitter canceller according to the present invention is applied, only sufficiently slow phase fluctuations are suppressed by the negative feedback type phase control loop, and phase fluctuations that are faster than the band of this phase control loop are suppressed by the jitter canceller. Division of suppressive functions is achieved. Furthermore, in the jitter canceller according to the present invention, if the instantaneous phase does not include a periodic component, the value of the prediction coefficient is kept almost zero.
No extra noise amplification effect occurs. Therefore, the remaining phase noise in the complex baseband signal supplied to the discriminator is only the in-band noise of the negative feedback phase control loop, but this amount can be reduced by narrowing the band by using the jitter canceller according to the present invention. Since it is proportional to the bandwidth of the phase control loop,
This significantly reduces the cost of a conventional system in which jitter is suppressed using only a phase control loop.

(Effects of the Invention) As described above, according to the present invention, a jitter canceller having highly accurate jitter suppression ability can be obtained, and its practical value is great.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a general embodiment of a jitter canceller according to the present invention, in which 103 is a register;
04 is a phase rotator, and 106 is an identification unit. 107 is a phase correction error detection unit, 108 is an accumulator, 109 is a complex trigonometric function generator, 111, 112°11
3 represents a load section, and 121, 122, and 123 represent correlators. FIG. 2 is a block diagram showing a configuration example. In the figure, 203 is a multiplier, 204,
307 is an adder, 205, 207°, 308 is a load section, 2
06.309 is a 1 sample concatenation circuit. 303 and 304 are polarity detectors, 305 is an exclusive OR circuit, and 306 is a selector. FIG. 4 is a circuit diagram showing a specific configuration example of the identification section and the phase correction error detection section when VSB is used as the modulation format, and FIG.
The figure is a circuit diagram showing a specific configuration example of the identification section and the phase correction error detection section when staggered QAM is used as the modulation format. In the figure, 403, 503, 504
, 605 is a discriminator, 404, 505, 506, 606 is a subtracter, 405° 507, 508, 607 is a multiplier, 6
03,604 represents a selector. FIG. 7 is a block diagram showing the basic configuration of a data reception system to which the jitter canceller according to the present invention is applied, in which 702 is a phase rotator, 703 is a voltage controlled oscillator,
04 is an instantaneous phase detector, 705 is an automatic equalizer, and 706 is a jitter canceller.

Claims (1)

[Claims] An instantaneous phase detecting means, an N-stage register into which the output of the instantaneous phase detecting means is sequentially input, and a phase prediction is performed by multiplying the outputs of each stage of the register by respective prediction coefficients, and then adding them all together. a predictor that generates a value, and a phase rotator that corrects a phase shift of a complex measpant signal according to the phase prediction value, and the prediction device that reduces the discrimination error power for the complex baseband signal after phase correction. A jitter canceller characterized by sequentially correcting coefficients.