JPS60173522A - Liquid crystal display device - Google Patents

Liquid crystal display device

Info

Publication number
JPS60173522A
JPS60173522A JP2990084A JP2990084A JPS60173522A JP S60173522 A JPS60173522 A JP S60173522A JP 2990084 A JP2990084 A JP 2990084A JP 2990084 A JP2990084 A JP 2990084A JP S60173522 A JPS60173522 A JP S60173522A
Authority
JP
Japan
Prior art keywords
voltage
common
sum
high level
low level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2990084A
Other languages
Japanese (ja)
Inventor
Yoshikiyo Futagawa
二川 良清
Kanemitsu Kubota
久保田 兼充
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Epson Corp
Original Assignee
Seiko Epson Corp
Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Epson Corp filed Critical Seiko Epson Corp
Priority to JP2990084A priority Critical patent/JPS60173522A/en
Publication of JPS60173522A publication Critical patent/JPS60173522A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To suppress a required power source at the two levels common with a logic circuit and to obtain the voltage waveform to increase an effective voltage ratio by adding a low level voltage to a segment signal when the logical multiple sum is odd for the period of >=2/3 of the same common timing period and a high level voltage thereto when said sum is even. CONSTITUTION:Three common lines (X,Y,Z) take the voltage levels to repeat periodically eight-ways of combinations (A,B,C) including (0,0,0), (0,0,1), (0,1,0), (0,1,1), (1,0,0), (1,0,1), (1,1,0), (1,1,1). On the other hand, the level taking the law of impressing a low level voltage V0 when the logical sum is odd and a high level voltage V1 when said sum is even is impressed to the segment line by 2/3 of the same common timing period when the logical sum (X+Y+Z)+(A+B+C) is ''1'' or ''0'' and another level is impressed for the remaining 1/3 thereto. The effective voltage to be impressed to a selection part is larger than in the prior art in this case as well.

Description

【発明の詳細な説明】 (技術分野) 本発明は液晶表示装置に係る。特に簡素化されたダイナ
ミック駆動する液晶表示装置に関する〇(従来技術) 従来の液晶表示装置用のダイナミック駆動回路は、一般
に2分め1バイアス法、3分の1バイアス法、N分の1
バイアス法が表示コントラストを向上させるに適した方
式として認められてきた。
DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a liquid crystal display device. Particularly related to a simplified dynamically driven liquid crystal display device (prior art) Conventional dynamic drive circuits for liquid crystal display devices generally use the 1/2 bias method, the 1/3 bias method, or the 1/N bias method.
The bias method has been recognized as a method suitable for improving display contrast.

第1図は電卓用液晶ディスプレイのダイナミック、駆動
波形として多く用いられている3分の1バイアス、5分
の1デユーティ−駆動の各端子の電圧波形である。この
波形は、ONセグメント部の実効電圧とOFFセグメン
ト部の実効電圧の比は1.91’5と比較的大きいが、
vQ + ”I H”2 Hv3の4電圧レベルが必要
になるため (1)各電圧レベルを昇圧、もしくは抵抗分割によ9作
る為、電力ロスを生ずる。従って、太陽電池駆動電卓の
ようにより小さく安価なバッチIJ−19に動の場合に
不利になる。
FIG. 1 shows voltage waveforms at each terminal for 1/3 bias and 1/5 duty drive, which are often used as dynamic and drive waveforms for liquid crystal displays for calculators. In this waveform, the ratio of the effective voltage of the ON segment part to the effective voltage of the OFF segment part is relatively large at 1.91'5,
Since four voltage levels of vQ + "I H" 2 Hv3 are required, (1) each voltage level is boosted or created by resistance division, resulting in power loss. Therefore, it is disadvantageous when using the smaller, cheaper batch IJ-19, such as a solar powered calculator.

(2)各電圧レベルが必要な為、駆動用回路として各出
力端子部に全てアナログスイッチを付ける為、その回路
負担も大きくなる。
(2) Since each voltage level is required, all analog switches are attached to each output terminal section as a driving circuit, which increases the circuit load.

(3)昇圧、電圧分割に対し、コンデンサー、抵抗等を
必要する為、電子部品のコストアップとなる。
(3) Capacitors, resistors, etc. are required for boosting and voltage division, which increases the cost of electronic components.

(4)最高電圧レベル(v3 )に対して点灯セグメン
トに印加される実効電圧が0.638V3と小さい為、
かなり高い電圧を供給する必要があり、ソーラー電卓の
場合には、ソーラーバッテリーの枚数が増加し、とれも
コストアップ要因となっていた。
(4) Since the effective voltage applied to the lighting segment is as small as 0.638V3 compared to the highest voltage level (v3),
It is necessary to supply a fairly high voltage, and in the case of solar calculators, the number of solar batteries increases, which is a factor in increasing costs.

(目 的) 本発明の目的は、必要電源はロジック回路部と共通の2
レベルにおさえるとともに実効電圧比を大きくする電圧
波形を提供し、上述した欠点を除去する事にある。
(Purpose) The purpose of the present invention is that the required power supply is two parts common to the logic circuit section.
The object of the present invention is to provide a voltage waveform that suppresses the voltage level and increases the effective voltage ratio, thereby eliminating the above-mentioned drawbacks.

(構 成) 本発明の液晶表示装置は、デユーティ比1:6のマルチ
プレックス駆動をせしめた液晶表示装置に於て、その表
示駆動のだめの印加電圧波形として、5本のコモンライ
ン(x、y、z)には各タイミング毎に電圧レベルの組
み合わせが(0,0+0)1(0+0+1)+(0+’
yO)+(0+’p’)p(’+ ロ 、ロ )、(1
,ロ 、1 ) 。
(Structure) The liquid crystal display device of the present invention uses five common lines (x, y , z), the combination of voltage levels at each timing is (0,0+0)1(0+0+1)+(0+'
yO)+(0+'p')p('+ ro, ro), (1
, ro, 1).

(1,1,口)、(1#1.1)、(ここで、1はハイ
レベル側電圧、0はローレベル側電圧を示す)になよう
に構成し、セグメントラインには各コモンラインに対し
て(ON又はOFF 、ON又はOFF 、ON又は0
FF)の8通りの組み合わせを(A、B、C)で表わす
としくA、B、Cはそれぞれ1又は0で表わし1はON
状態を、0ははOFF状態を示す)、(X* Y+ z
)= (Ar1.C)の時にはローレベル電圧を、(x
、y。
(1, 1, mouth), (1#1.1), (where 1 indicates the high level side voltage and 0 indicates the low level side voltage), and each common line is connected to the segment line. for (ON or OFF, ON or OFF, ON or 0
The 8 combinations of FF) are represented by (A, B, C), and A, B, and C are each represented by 1 or 0, and 1 is ON.
state, 0 indicates OFF state), (X* Y+ z
) = (Ar1.C), the low level voltage is set to (x
,y.

” )= (A+ Bt C)の時にはハイレベル電圧
を印加し、それ以外の時には論理多数和(x+y+Z十
A十B+C)が奇数の時にはローレベル電圧を、偶数の
時にはハイレベル電圧を少なくとも同一コモンタイミン
グ期間の3分の2以上の期間セグメント信号に加えたも
のである。
) = (A+BtC), apply a high level voltage, otherwise apply a low level voltage when the logical majority sum (x+y+Z0A0B+C) is an odd number, and apply a high level voltage when it is an even number. This is in addition to the segment signal for a period of two-thirds or more of the timing period.

(実施例) 第2図は、本発明に基づく2つのレベルだけで構成した
3分の1デユーテイのマルチプレックス駆動用の電圧波
形例である。
(Embodiment) FIG. 2 is an example of a voltage waveform for a 1/3 duty multiplex drive configured with only two levels based on the present invention.

その波形組み合わせのルールは以下の通りである□今、
3本のコモンライン、コモン1.コモン2、コモン5の
状態を(X、Y、z)で表現すると(X又はY又は2=
0の時にはロー電圧レベルvoを示し、X又はY又はZ
=1の時にはハイ電圧レベルv1を示す)、1フレーム
もしくは正負2フレームの間にx、y、zの組み合わせ
が必らず (ロ 、ロ 、 0 )、 (0、0、1)
 l (0’、 1 t−5= 0)+(CI+1.1)+(1+”+ 0)s(1+口
・1)+(’l’IO)+(’l’91)の8通りが生
ずるように電圧波形を組む。この際、組み合せ順序は任
意でよい。
The rules for the waveform combination are as follows.□Now,
3 common lines, common 1. Expressing the states of common 2 and common 5 by (X, Y, z), (X or Y or 2 =
When it is 0, it indicates a low voltage level vo, and when it is X or Y or Z
= 1 indicates a high voltage level v1), the combination of x, y, z is not necessarily present between one frame or two positive and negative frames (Ro, Lo, 0), (0, 0, 1)
There are 8 ways: l (0', 1 t-5 = 0) + (CI + 1.1) + (1 + " + 0) s (1 + mouth・1) + ('l'IO) + ('l'91) The voltage waveforms are assembled so that the voltage waveforms are generated.At this time, the order of combination may be arbitrary.

一方、それに対するセグメントラインの駆動電圧波形は
対コモン1 、2s、 3に対する選択(点灯ON状態
)か非選択(点灯OFF状態)によって8通シの組み合
わせが考えられるが各々の組み合わせに対し第1表の様
に組み合わせる。表中のHはハイレベル側電圧(V 1
) ヲ示し、Lはローレベル電圧(V、)を示す。
On the other hand, the driving voltage waveform of the segment line for this can be considered to have 8 combinations depending on the selection (lighting ON state) or non-selection (lighting OFF state) for the commons 1, 2s, and 3. Combine as shown in the table. H in the table is the high level side voltage (V 1
), and L indicates a low level voltage (V, ).

 6− 第 1 表 第1表に於て(A、B、a)=(o、o、o)のケース
はそのセグメントラインが、コモン1゜2.3のいずれ
に対しても非選択(非点灯)の場合を示し、(A 、B
、0)=(0,0、1)の場合には、そのセグメントラ
インはコモン1と2に対しては非選択(非点灯)、コモ
ン3に対しては選択(点灯)のケース、(A、B、O)
:(1。
6- Table 1 In the case of (A, B, a) = (o, o, o) in Table 1, the segment line is not selected (non-selected) for any of the commons 1° and 2.3. (lit), (A , B
, 0) = (0, 0, 1), the segment line is non-selected (not lit) for commons 1 and 2, selected (lit) for common 3, (A ,B,O)
:(1.

1.1)のケースはそのセグメントラインはコモン1,
2.3いずれに対しても選択(点灯)の場合を示す。第
1表に基づいて表わした波形例が第2図に示しである。
In the case of 1.1), the segment line is common 1,
The case where both 2.3 are selected (lit) is shown. An example of the waveform expressed based on Table 1 is shown in FIG.

例えばセグメントラインカコモ71,2,517C対し
くoyy、oyF、oyp)つ捷り(0,0,0)の場
合には各コモンの組合わせに対し時間的K(x、y、z
)が(1,1゜1)→(−0、0、0)方間にH−+)
l→H−+L−+H→L→L−+L11Ii:なってい
る。
For example, in the case of segment line Kakomo 71, 2, 517C and oyy, oyF, oyp) switching (0, 0, 0), the temporal K(x, y, z
) is H-+ in the (1,1°1) → (-0, 0, 0) direction
l→H-+L-+H→L→L-+L11Ii:

この規則性は、優先度の高い順に (1) (X 、 Y 、 Z ) = (A 、 B
 、 O)ならばL(ローレベル電圧:Vo)を印加す
る。
This regularity is expressed as (1) (X, Y, Z) = (A, B
, O), then L (low level voltage: Vo) is applied.

(2L (X、Y、Z)=(A、B、O)ならばH(ハ
イレベル電圧:VI)を印加する。
(2L If (X, Y, Z) = (A, B, O), apply H (high level voltage: VI).

(3) 上記以外の場合には 論理和(x+y十z )+(A十B+O)が奇数の時に
はL(ローレベル電圧:Vo)を、偶数の時にはH(ハ
イレベル電圧;V、)を印加する。
(3) In cases other than the above, apply L (low level voltage: Vo) when the logical sum (x+y1z)+(A0B+O) is an odd number, and apply H (high level voltage; V,) when it is an even number. do.

以上の規則性で第1衣に示した波形のロジックを形成す
る。
The above regularity forms the waveform logic shown in the first layer.

本発明による駆動の実効電圧を計算すると、選択部(O
N部)に印加される実効゛電圧(VON )はVt −
Vo =vとして VON:Jr¥−v=Q、866v 非選択部(OFF部)K印加される実効電圧(VOFF
 )は VOFF = JT V = [15V従って実効電圧
比VON/VOFFは voM/Vory =ig = 1.732この数値全
従来の駆動法と比較すると、いずれも3分の1デユーテ
イの場合で、第2表の通りとなる。
When calculating the effective voltage of the drive according to the present invention, the selection part (O
The effective voltage (VON) applied to the N section is Vt -
As Vo = v, VON: Jr\-v = Q, 866v Effective voltage applied to non-selected part (OFF part) K (VOFF
) is VOFF = JTV = [15V Therefore, the effective voltage ratio VON/VOFF is voM/Vory = ig = 1.732 Comparing this value with the conventional drive method, both cases are 1/3 duty, and the second It is as shown in the table.

第 2 表  9− 第3図は、本発明の他の具体的な駆動波形で、この場合
には、コモンラインは前述の実施例と同じ[3本のライ
ンが(0,0,0)、(0,0゜1)、(0,1,0)
、(0,1,1)、(1゜0.0)、(1,0,1)、
(1,1,0)、(1,1,1)の8通りの組み合わせ
を周期的に繰り返す電圧レベルを取る。一方セグメント
ラインは(X、Y、Z)=(A、B、O)の場合と(X
 、 Y 、 Z ) = (’ A−、13、O)の
場合には前実施例と同じであるが、それ以外の論理和(
X十Y−1−Z )+(A十B−1−0)が1又は00
時には、同一コモンタイミング期間の6分の2だけ前実
施例の規則を取ったレベルを印加し、残りの3分の1は
もう一方のレベルを印加する。この場合の各実効電圧及
びその比は VON =n V = 0.816 VVow F =
/V :0577V voN/Voyy = p = 1.414である。
Table 2 - Figure 3 shows another specific driving waveform of the present invention, in which the common line is the same as in the previous embodiment [three lines are (0, 0, 0), (0,0°1), (0,1,0)
, (0,1,1), (1°0.0), (1,0,1),
A voltage level is taken that periodically repeats eight combinations of (1, 1, 0) and (1, 1, 1). On the other hand, the segment line has two cases: (X, Y, Z) = (A, B, O) and (X
, Y, Z) = ('A-, 13, O), it is the same as the previous example, but for other logical sums (
X0Y-1-Z)+(A1B-1-0) is 1 or 00
Sometimes, for two-sixths of the same common timing period, a level following the rules of the previous embodiment is applied, and for the remaining one-third, the other level is applied. In this case, each effective voltage and its ratio are VON = n V = 0.816 VVow F =
/V :0577V voN/Voyy = p = 1.414.

この場合にも70Mの実効電圧を従来法に比し大−10
− きくなる。
In this case as well, the effective voltage of 70M is significantly lower than that of the conventional method.
- become louder.

なお、本発明の技術的思想を拡大し、具デユーティ、具
デユーティ、見デユーティ・・・・・・等で駆動するこ
とも勿論可能である。4た、本発明はセグメント型、マ
トリックス型いずれにも適用できる。
Note that it is of course possible to expand the technical idea of the present invention and drive with a tool duty, tool duty, viewing duty, etc. 4. The present invention can be applied to both segment type and matrix type.

(効 果) 次に本発明の効果を整理すると (1) 供給!圧しベルが2本でよいため、−電源で論
理回路と液晶表示体駆動電源が兼用できる。従って、6
レベル、4レベルヲ作る為の昇圧もしくは抵抗分割が不
必要にな9、電力の無駄使い並びに、その為のコンデン
サー。
(Effects) Next, the effects of the present invention can be summarized as follows: (1) Supply! Since only two pressure bells are required, the negative power supply can serve both as the logic circuit and the liquid crystal display drive power supply. Therefore, 6
Step-up or resistance division to create 4 levels is unnecessary. 9. Wasted power and capacitors for that purpose.

抵抗等の電子部品を節約できる。Electronic components such as resistors can be saved.

(2)供給電源電圧vVc対する点灯実効電圧が高い(
0,8/+6V)為、比較的低電圧電源で、液晶表示体
が駆動できるため、電池個数が少なくて済む。特に太陽
電池駆動の場合には太陽電池のパネル枚数を節約できる
(2) The effective lighting voltage with respect to the supply power supply voltage vVc is high (
0.8/+6V), the liquid crystal display can be driven with a relatively low voltage power supply, so the number of batteries can be reduced. Particularly in the case of solar battery drive, the number of solar battery panels can be saved.

(3)以上の事により現時点の到達技術から、本発明の
駆動法を用いる事によシ、昇圧なしの1.5v電源駆動
表示の液晶表示装置を提供する事が可能になり低電圧、
低電力化が図られ、特に電卓9時計のコストダウン、バ
ッテリーの長寿命化を可能にする。
(3) Based on the above-mentioned technology, by using the driving method of the present invention, it is possible to provide a liquid crystal display device driven by a 1.5V power supply without boosting the voltage.
The power consumption is reduced, making it possible to reduce the cost of calculators and watches in particular, and extend the lifespan of batteries.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は6分の1デユーテイ、5分の1バイアスによる
従−来のダイナミック駆動の電圧波形例。 第2図は本発明に基づく、3分の1デユーティ−の液晶
表示装置の駆動電圧波形実施例。 第3図は本発明による他の実施例。 以上 出願人 エプソン株式会社 代理人 弁理士最上 務 第1図 VS :Jt:zl (OFF ) VS ″モレ2 (OFF) vs コモン+ (ON) Vj コモンz −コー(OFF) vs コモン” (OFF) tfj>MON、ON、OFF>Y;”9.っ〜1 μ
の一一一一脇ア(ON)VS a72 (ON ) vs コモンl (ON) !S コモン2 (ON ) vs コモンJ (ON ) 第2図
Figure 1 shows an example of the voltage waveform of a conventional dynamic drive with a 1/6 duty and a 1/5 bias. FIG. 2 is an example of a driving voltage waveform of a 1/3 duty liquid crystal display device based on the present invention. FIG. 3 shows another embodiment according to the present invention. Applicant Epson Corporation Agent Patent Attorney Mogami Figure 1 VS :Jt:zl (OFF) VS ``Mole 2 (OFF) vs Common + (ON) Vj Common z -Co (OFF) vs Common'' (OFF) tfj>MON, ON, OFF>Y;”9.~1μ
1111 side a (ON) VS a72 (ON) VS common l (ON)! S Common 2 (ON) vs Common J (ON) Fig. 2

Claims (1)

【特許請求の範囲】 デユーティ比1:5のマルチプレックス駆動をせしめた
液晶表示装置に於て、その表示駆動のための印加電圧波
形として、3本のコモンライン(x、y、z)には各タ
イミング毎に電圧レベルの組み合わせが(口+0+0)
t(”+”+’)+(”+’+ 0 )+(ロ + ’
 s ’ ) * (’+”+ OL(’+0+’)+
(’+’+0)+(1+1+’)+(ここで、1はハイ
レベル側電圧、0はローレベル側電圧を示す)になるよ
うに構成し、セグメントラインには各コモンラインには
各コモンラインに対して(ON又はOFF、ON又はO
FF、ON又は0FF)の8通りの組み合わせを(A、
B。 C)で表わすとしくA、B、Cはそれぞれ1又は口で表
わし1はON状態を、0はOFF状態を示す)、(X、
Y、Z)−(A、B、C)の時にはローレベル電圧を、
(X+ Y+ z)= (A+ BrC)の時にはハイ
レベル電圧を印加し、それ以外の時には論理多数相(X
+Y+Z+A+B+C)が奇数の時にはローレベル電圧
を、偶数の時にはハイレベル電圧る少なくとも同一コモ
ンタイミング期間の3分の2以上の期間セグメント信号
に加えた事を特徴とする液晶表示装置。
[Claims] In a liquid crystal display device that uses multiplex drive with a duty ratio of 1:5, the three common lines (x, y, z) have three common lines (x, y, z) as applied voltage waveforms for display drive. The combination of voltage levels for each timing (mouth + 0 + 0)
t("+"+')+("+'+0)+(ro+'
s' ) * ('+”+ OL('+0+')+
('+'+0)+(1+1+')+(here, 1 indicates the high level side voltage and 0 indicates the low level side voltage), and each common line has each common line on the segment line. For the line (ON or OFF, ON or O
FF, ON or 0FF) in 8 combinations (A,
B. (X,
At the time of Y, Z) - (A, B, C), low level voltage,
When (X+ Y+ z) = (A+ BrC), a high level voltage is applied, and at other times, a logical majority phase (X
+Y+Z+A+B+C) is an odd number, a low level voltage is applied to the segment signal, and when it is an even number, a high level voltage is applied to the segment signal for at least two-thirds or more of the same common timing period.
JP2990084A 1984-02-20 1984-02-20 Liquid crystal display device Pending JPS60173522A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2990084A JPS60173522A (en) 1984-02-20 1984-02-20 Liquid crystal display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2990084A JPS60173522A (en) 1984-02-20 1984-02-20 Liquid crystal display device

Publications (1)

Publication Number Publication Date
JPS60173522A true JPS60173522A (en) 1985-09-06

Family

ID=12288851

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2990084A Pending JPS60173522A (en) 1984-02-20 1984-02-20 Liquid crystal display device

Country Status (1)

Country Link
JP (1) JPS60173522A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62232620A (en) * 1986-04-02 1987-10-13 Sharp Corp Liquid crystal display device
US6597119B2 (en) 1998-02-23 2003-07-22 Seiko Epson Corporation Method for driving an electro-optical device, driving circuit for driving an electro-optical device, electro-optical device, and electronic apparatus

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62232620A (en) * 1986-04-02 1987-10-13 Sharp Corp Liquid crystal display device
US6597119B2 (en) 1998-02-23 2003-07-22 Seiko Epson Corporation Method for driving an electro-optical device, driving circuit for driving an electro-optical device, electro-optical device, and electronic apparatus

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