JPS6054678B2 - voltage divider circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION When three or more potential levels are required, such as in a dynamic (dynamic or scanning) liquid crystal drive circuit, the present invention provides a method for controlling the potential between the highest potential and the lowest potential. There are some related to voltage divider circuits for obtaining

In recent years, in various digital electronic devices such as electronic desktop calculators, electronic circuits have been integrated with so-called complementary circuit configurations formed using both P-type and N-channel 1G-FETs (MOS transistors). Furthermore, there is a strong demand for lower power consumption and smaller sets by using liquid crystals (abbreviated as ``liquid crystals'') as display devices.

For example, electronic wristwatches that do not require battery replacement for 1 to 2 years have been commercialized, and even calculators have a usage time of 1,000 to 1,000 yen.
Products that do not require battery replacement for about 50 seconds have been commercialized.
On the other hand, due to its chemical properties, it is important to apply alternating current voltage to the LC, which has excellent low power consumption, and to reduce the integrated voltage component to zero, in order to extend its life.

By the way, one electrode of multiple fields segments is made common (
For example, for each display digit), the other electrode of the segment is shared between different segment groups in which the one electrode is shared, and each segment group in which the one electrode is shared is selectively scanned in a time-division manner. In the dynamic driving method, since the response speed of the LC is extremely slow compared to other display devices, driving signals with three or more voltage levels are usually required when dynamically driving the LC. For this reason, this driving signal is obtained from outside the integrated circuit, but this circuit consumes a large amount of power, and (1) the excellent characteristics of low power consumption of the display device cannot be fully utilized. In addition, as part of the miniaturization and cost reduction of digital electronic devices, there is a strong demand to reduce the number of individual components, but among the three or more voltage levels, the voltage level between the highest and lowest level is removed from the integrated circuit. Therefore, it was difficult to reduce the number of individual parts.
The present invention has been made in view of the above circumstances, and by making it possible to obtain within the integrated circuit a voltage level between the highest voltage level and the lowest voltage level used within the integrated circuit, power consumption can be reduced and the number of individual components can be reduced. The purpose of this invention is to provide a voltage divider circuit that can reduce the voltage.

Embodiments of the present invention will be described below with reference to the drawings.

In the following explanation, a low level (upper o level) is considered to be established (also referred to as logic ゜"1" or set), and a high level (ground level) is considered to be not established (also referred to as logic ゜゛0゛ or reset). Figure 1 shows the 113 duty (Duty) of the LC dynamic drive method.
, 113 LC using prebias method
This is an example of the connection of the display section. Here, the display digit is 1 on a calculator etc.
A case is shown in which the digit is composed of 8 segments (7 segments arranged in a Japanese character shape and 1 segment for the decimal point). Fig. 2 is an equivalent circuit diagram of the liquid crystal segment in Fig. 1, Fig. 3 is a signal waveform diagram for driving the LC of Fig. 1, and Fig. 4 is a calculator etc. using the circuit of one embodiment of the present invention. FIG. In Fig. 2, CLO indicates pressure capacity and RLC indicates pressure leak resistance.Capacitance CLC is usually several PF to several tens of pF per segment, and leak resistance RLO is 10 pF.
It is 0MΩ or more.

In FIG. 4, reference numeral 10 denotes a power source, which is connected to a high potential power source end 11 and a low potential power source end 15, which are power receiving ends. The low potential is set to the upper o [V] level.

20 is a logic section that operates between the ground level and the upper O level, and this logic section includes a basic timing generation circuit for LC display, a decoder circuit that converts the data signal in the BCD code into a segment drive signal for each country, a calculator, etc. It consists of the calculation part of a computer or the timekeeping circuit of a watch.

30 is a voltage dividing circuit, and this circuit 30 is connected to the terminal 11.
, 15, the first resistor and the first switching means (M
(OS transistors) are connected in series, and a second resistor is connected in parallel to the series circuit to form a unit, which is connected in four single-position columns.

Each of the above units is indicated by U1 to U4, the first resistor is Rll to Rl4, the first switching means (transistor) is Pl, P2, N2, Nl, and the second resistor is R
2l to R24. The gates of the P-channel transistors Pl and P2 are supplied with a pulse φ, which will be described later, from the circuit 20.
, and an inverted pulse d of the pulse φ is applied to the N-channel transistors Nl and N2 via the inverter 21, and −(EO, −μE) is applied from the connection terminals 12, 13, and 14 between the units. , 1 T. Further, reference numeral 40 is a J°C drive which generates a signal H1″H39α11′α89β1ゞβ89γ11′γ8 for driving the display section 50 as shown in FIG. This circuit 40 receives each signal h1 to H3, W from the logic section 20.
etc., and uses a circuit group consisting of the ground potential, the upper O potential, and three potentials derived from the voltage divider circuit 30, such as a phase inverter 41 as shown in FIG.
1ゞα89β1ゞβ89γ1ゞγ8 A circuit that outputs signals H1 to H3 (here only a circuit that obtains H1 is shown) using a circuit such as the one shown in FIG. ). Next, before explaining the operation of the voltage dividing circuit 30, the operation of each waveform J° C. in FIG. 3 will be explained.

φL is a pulse generated for a certain period of time at the start of one display cycle, and defines one cycle of display. The desirable period of the pulse φL varies depending on the characteristics of (1), etc., but is generally considered to be 2.47 nsec. This φ,
The pulse width of 2 is determined by the circuit configuration in the logic section 20 or the characteristics required of the circuit 30.
It is assumed to be 5 μSec. Hl, h2, h3 are scanning pulses Hl
, H2, and H3. For example, when the pulse h1 is established, the pulse H1 is set to the selection level (0 [■] to 1 EOCV)), and when the pulse h1 is not established, the pulse H1 is set to the non-selection level (-VMN=mmE). W is a pulse that specifies the polarity of the selection level and also specifies the polarity of the segment signal when the scanning timing of pulses H1, H2, and H3 is reached by H1, h2, and h3. That is, when the pulse w is established, the selection level of the pulses H1, H2, and the ratio is O [■], and when the pulse w is not established, the selection level of the pulses H1, H2, and H3 is O [■]. Each segment signal is at the 66-' level, that is, one level, when the pulse w is established during the corresponding display cycle. The level is the display level, the 66+'1 level, that is, the -1E0 level, is the non-display level, and when the pulse w is not established, it is the -' level, that is, the state. Each segment is driven as a display level with level 66+13, ie -(EO).
α1-19α1-29α1-3) Segment signal α1
The voltage applied to each segment when the segment SE1 of the first digit in Fig. 1 is in the non-display state and the segments SE4 and SE7 are in the display state by scanning pulses Hl, H2, and H3 is calculated based on the common terminal. This is what is shown. In other words, the applied voltage is different in terms of timing. Segments alternated by [V] are displayed, and segments alternated by (EO [■]) are not displayed.The conditions required for the LC drive waveform are that LC has a leak resistance per segment. RLC is usually 100MΩ or more and several PF to several 1
Since it has a capacitance of 0 pF, firstly, the output resistance of each level should be one that can sufficiently compensate for leakage current by RLC.

That is, if RLc = 300 MΩ, it can be increased to about 400 kΩ, which is sufficiently small compared to 10 MΩ, and the segment signals α1 to α8, β1 to β8, γ1 to γ
Each output resistor of 8 may be a higher resistor. The second condition is that the LC is capacitive so that each drive signal can successfully switch the LC capacitance during switching.
That is, if the capacitance CLO is 30 pF, the pulses H1 to H3 in FIG. 1 need to drive a capacitance of about 1000 PF, so the output resistance needs to have a sufficiently low resistance. For example, pulse H1 to H3. Assuming that the output impedance for the positive level is 400 kΩ, which is much larger than the output impedance for other levels, the operating waveforms of the pulses H1 to H3 are -b and E in FIG. Switching to the level will result in the state shown by the dotted line. The delay time constant shown by this dotted line is 400kΩ×1000
pF=400 μSec, and due to this delay, the states of the segment applied voltages α1-1, α, -2, α1-3 still have dotted line waveforms. As a result, the segment SE1 in FIG. 1, which is originally in a non-display state, is not displayed, that is, it is not completely displayed, but is displayed in a weak display state, which is extremely inconvenient. The present invention takes into consideration the improvement of such problems, and it will be fully understood from the following description that it is possible to make the country operate stably. Note that the output resistance for the LC drive signal is represented by the sum of the internal resistance of the power supply source and the output resistance of the main drive circuit, but the output resistance of the drive circuit varies depending on the dimensions of the elements constituting the circuit, such as MOS transistors. It can be easily increased or decreased, and can be considered negligible compared to the internal resistance of the power supply source. Figure 7 is the 4th
This is an equivalent circuit of the voltage dividing circuit 30 shown in the figure.

That is, resistance Rll=Rl. =Rl3=Rl4=-40k
Ω, and the on-resistances of transistors Pl, P2, N2, and Nl are set to a small value that can be ignored with respect to the above resistance value, or the sum of the on-resistance of transistor P1 and Rll, P
The sum of the on-resistance of 2 and Rl2, the sum of the on-resistance of N2 and Rl3, and the sum of the on-resistance of N1 and Rl4 are all the same resistance value 40
You can think of it as kΩ. And R2l=R23=R24
:400kΩ, transistors Pl, P2, Nl
, N2 are both on, the switches SW-1 to SW-3 are closed, and when the transistors Pl, P2, Nl, and N2 are all off, the switches SW-1 to SW-3 are open. According to Thevenin's theorem, the fourth It will be easily understood that the circuit 30 shown in the figure is as shown in FIG. Here, the power supply 10 is (EO[■
] is shown as a series circuit of batteries 10-1, 10-2, 10-3, 10-4, and the output voltage (-)EOCV of the output terminal 12 is
]) is the internal resistance for transistors Pl, P2, N
When l and N2 are both turned on, the parallel resistance is 30kΩ and 300kΩ, and when both transistors are turned off, the resistance is 300kΩ. Also, the internal resistance to the output voltage (upper EOCV) of the output terminal 13 is 40 kΩ when the transistor is on.
and a parallel resistor of 400 kΩ, 4 when the transistor is off.
00kΩ, and the output voltage of the output terminal 14 (1t.
Cv]) is a parallel resistance of 30 kΩ and 300 kΩ when each transistor is on, and 300 kΩ when the transistor is off. Transistor P, P2
, Nl, N2 at least at the start of one display cycle of LC. In order to turn on these transistors for a certain period of time, the gates of transistors Pl and P2 are supplied with 25 μS from the logic section 20 at the beginning of one display cycle.
A pulse φ having a pulse width of ec is applied, and a pulse DL which is the complement of φ is applied to the gates of transistors Nl and N2. Therefore, the switch for each field drive signal is 1-
Ke. Regarding the switch to [■], the time constant is 40μSec because it drives 1000pF with an output resistance of 40kΩ.
2-) Regarding the switch to EO [V] or 0 [V], since 1000 pF is driven with an output resistance of 30 kΩ, the time constant is 30 μSec, and shows good characteristics in response to ゜6 display leakage. It turns out. And the pulse φ,
is not established, and when FET Pl, P2, Nl, and N2 are turned off, each output level is slightly lower than 1. - [V] or -
JEO or Ittsutsumi. [■] On the level
44, even if the resistance is 400k as shown in Figure 7.
Ω, 300 kΩ, and 300 kΩ are switched to each level, and these resistors compensate for the leakage current of the LC to stably drive the LC.

In the case of a dynamic display method, the power supply voltage EO is usually 2.
5 to 10 [V] is used, but 3.0 [V] or 4.5 [V] is often used to reduce power consumption.

Now E. If the current consumption of the voltage divider circuit 30 is determined by assuming that = -4.5 [V], the average current is approximately 3.3 μA.
On the other hand, in a calculator, the current consumption of the logic section 20 is generally expressed as
Since it is about 0 μA to 200 μA, the current consumption required for dynamic driving of the LC can be ignored compared to the current consumption in the logic section 20, which is effective for energy saving. In recent years, ion implantation technology has been introduced to the production of integrated circuit chips, so one major surface of a semiconductor is doped with low impurity concentrations.
Moreover, since a shallow semiconductor layer of about 1000A to about 1μ can be stably formed, each resistor in the voltage divider circuit 30 can be connected to the logic section 20 or (1) drive circuit 4 regardless of its size.
Since it can be stably integrated on the same chip as 0, it is extremely effective in downsizing electronic devices and further reducing the number of lead terminals of integrated circuits, improving characteristics (reliability) and reducing costs. Note that the arrangement of each transistor in Fig. 4 is not limited to the case shown in the figure, and the connection order of the resistor and transistor may be reversed, but considering the operating characteristics of each transistor, the arrangement of each transistor as shown in the figure is It is desirable to arrange it closer to the output end 11 or 15.

For example, for the transistor P2, the pulse BL
For example, for transistor N2, pulses φ,
Modifications such as replacing with a P-channel type transistor P3 having a gate input as input, or replacing with a parallel circuit of N2 and P3 are possible as long as the switching characteristics of each drive signal can be guaranteed. FIG. 8 shows an embodiment that has even better low power consumption characteristics.

That is, the current consumption is reduced by forming the resistors R2l, R22, R23, and R24 into series circuits with transistors serving as other switching elements.
For example, a P-channel transistor P4 is connected in series to the resistor R2l with a pulse φ'' as its gate input, a P-channel transistor P5 is connected in series with the resistor 1922 and its gate input is a pulse φ''5, or a pulse b'' is input as its gate. An N-channel transistor or a parallel circuit thereof is provided, and the N-channel transistor N4 is connected in series to the resistor R24 with a pulse ↓'' as its gate input, and the pulse b''6 is connected in series to the resistor R23 as its gate input. An N-channel transistor N5, a P-channel transistor whose gate input is pulse φ'', or a parallel circuit thereof is provided. In this way, the transistors P4, P
5, N4, and N5 are off, resistors R2l to R2
Since no current flows through 4, the power supply voltage is E. =4.5 [V]
The current consumption can be reduced to about 0.5 μA or less.
In the embodiments shown in FIGS. 4 and 8, for example, a resistor R2l or a series circuit of a transistor P4 is provided in parallel with a series circuit of a resistor Rll and a transistor P1. The series circuit may be connected in parallel only to the transistor P1.

The same holds true for resistor R22 or resistor R22 and transistor P5, resistor R23 or resistor R23 and transistor N5, and resistor R24 or resistor R24 and transistor N4. In each of the above embodiments, four unit units were used to obtain three divided potentials, but the number of units was n.
By using (n=3, 4, 5,...)
It is also possible to obtain ゜n-1゛ divided potentials.

That is, for example, two divided potentials obtained by dividing upper o into three equal parts -AEO
Toke. Or get resistance Rll=Rl. =Rl3+R
By setting l4, R2l=R22=R23+R24, one EO is obtained at the terminal 12 -AEOl, one at the terminal 13, and one at the terminal 14. It is also possible to obtain the potential of FIG. 9 uses four potential levels with a duty of 113, and L
10 shows the operating waveform (pulses h1 to H3, φ, not shown). That is, in each of the above embodiments, the unit U1
A P-channel transistor PIO whose gate input is an inverted pulse of the polarity specifying pulse w is connected in parallel to the unit U4, and an N-channel transistor NIO whose gate input is the pulse W is connected in parallel to the unit U4. 1
The potential level of 4 changes with the same polarity as the pulse w, as shown in FIG. Therefore, a pulse pulse is established and the transistor P
l. The on-resistance when is on is resistors Rl2, Rl3, Rl
4, the pulse W is not established and the transistor N
The on-resistance when lO is on is the resistance Rll, Rl2, R
It is smaller than the sum of l3. The circuit configuration of the LC drive circuit 40 in this case may be the configuration described in FIG. 4. 1st
FIG. 1 shows an embodiment aimed at further reducing the power consumed for field display.

That is, the normal (1) display state is changed to all cells after a certain period of time.
In order to enter a predetermined specific display state, such as lighting or non-lighting, the circuits of each unit U1 to U4 are closed for a certain period of time to bring the normal display state to the above, as shown in Figure 5. and at least one switching means (transistor) P2O for opening during other periods.
By interposing the voltage divider, the power consumption in the voltage dividing circuit during a specific display state period is maintained at about the level of leakage current. Here, the control signal T, which is one means for bringing the LC into a specific display state, is obtained within the logic section 20 of FIG. 4 using a timer circuit, a frequency dividing circuit, etc. However, when the signal T is established, a normal display state is established, and when the signal T is not established, a specific display state is established. Figure 12 shows the signal T and the corresponding terminals 12 to 14.
This is a diagram showing the potential state of . In this case, as shown in FIG. 12, when the signal T is reset, the terminal 12 is connected to Gnd.
Since the level (ground) and terminals 13 and 14 are both at the upper O level, in order to make the integrated value of the voltage applied to each W segment zero at the time of reset of this signal T, the drive shown in Figs. 5 and 6 is required. This is done by controlling the input signal of the circuit using the signal T, 〒 or W, ;

For example, instead of pulses Hl, h2, h3 and their inverted pulses as drive circuit inputs of scanning pulses Hl, H2, H3, respectively ゛゜h1+〒゛, "H2+〒゜゛, "゜h3+〒゛ and their inverted pulse Then, only when the signal T is reset, the pulses H1, H2, and H3 each operate between the ground and the upper O level, and output the inverted level of the signal w. Therefore, in this case, if the signal w is introduced as an input to the segment signal drive circuit, the drive circuit will be connected to the ground and the upper
By outputting the inverted level of the signal w having the level, the national segment to which the segment signal is applied can be effectively hidden. On the other hand, if the signal W is introduced as an input to a segment drive circuit, the drive circuit outputs the same pulse as the signal w having the ground and upper O levels, and all LC segments to which the segment signal is applied are brought into a good display state. can do. Alternatively, pulse Hl
, H2, and H3 are fixed to either the ground or the upper O level when resetting the signal T, and the outputs of all segment signal drive circuits are fixed to the same level as the pulses H1, H2, and R, thereby reducing the applied voltage of all segments. By constantly setting the value to zero, all segments can be satisfactorily kept in a non-display state. As explained above, according to the present invention, switching means are inserted in series with each resistor series circuit provided between a pair of potential supply sources, and the switching means are turned on and off. Appropriate LC driving is possible, and each resistor and switching means can be incorporated into an integrated circuit together with other circuits, so a voltage dividing circuit is provided that facilitates miniaturization of the device and integration of the circuit. It is possible.

[Brief explanation of the drawing]

The figures are for explaining the embodiments of the present invention. Figure 1 is a wiring diagram of the LC display section, Figure 2 is an equivalent circuit diagram of the same part, and Figure 3 is an equivalent circuit diagram of the same part.
1 is a timing chart showing the operation of FIG. 1, FIG. 4 is a circuit diagram showing an embodiment of the present invention, and FIGS. 5 and 6 are (1)
) FIG. 7 is an equivalent circuit diagram of the voltage division circuit section of FIG. 4, FIGS. 8 to 9 are circuit diagrams of other embodiments of the present invention, and FIG. 9 is a timing chart showing the operation, FIG. 11 is a circuit diagram of still another embodiment of the present invention, and FIG. 12 is a timing chart showing the operation of the same circuit. 11, 15...Power terminal, 12-14...
...Output terminal, 20...Logic section, 30...
...Voltage divider circuit, 40...LC drive circuit, 5
0...Pressure display section, Rll~Rl4...Low resistance, R2l~R24...High resistance, Pl, P29Nl9
N29P49P59N49N59PlO9NlO9P2
O...MOS transistor.

Claims (1)

[Claims] 1. A unit comprising a series circuit in which a first resistor and a first switching means are connected in series, and a second resistor in parallel with the series circuit or the first switching means. A circuit formed by connecting three or more of these units in series between first and second potential supply terminals as a unit, a voltage output terminal respectively derived from the series connection terminal between the units, and each of the first switching terminals. 1. A voltage divider circuit comprising: means for simultaneously turning on or turning off the means. 2 A series circuit in which a first resistor and a first switching means are connected in series is provided, and a series circuit of a second resistor and a second switching means is provided in parallel to the series circuit or the first switching means. a circuit formed by connecting three or more unit units in series between first and second potential supply terminals; a voltage output terminal respectively derived from the series connection terminal between the respective units; 1. A voltage dividing circuit comprising: means for simultaneously turning on or off one switching means; and means for turning on or off each second switching means simultaneously. 3. A unit comprising a series circuit in which a first resistor and a first switching means are connected in series, and at least a second resistor in parallel with the series circuit or the first switching means. a circuit comprising four units connected in series between the first and second potential supply terminals; a second switching means connected in parallel to the first unit counted from the first potential supply terminal; a third switching means connected in parallel to the first unit counted from the potential supply end of the unit, a voltage output end respectively derived from the series connection end between the units, and each of the first switching means. means for simultaneously turning on or off; and a second;
and means for alternately turning on the third switching means. 4 A series circuit in which a first resistor and a first switching means are connected in series is provided, and at least a second resistor is provided in parallel to the series circuit or the first switching means. 3 credits or more 1st and 2nd
a series circuit connected in series between the potential supply terminals of and a second switching means inserted in series with the series circuit;
It is equipped with voltage output terminals respectively derived from the series connection terminals between the units, means for simultaneously turning on or off each of the first switching means, and means for controlling the second switching means on or off. A voltage divider circuit characterized by: