JPS60172823A - Amplifier - Google Patents

Abstract

PURPOSE:To realize easily an A/D converter with high conversion accuracy by using a circuit having a signal transmission characteristic not affected by the fluctuation of a power supply voltage and the operating current to amplifiers connected in cascade in a cascade type A/D converter. CONSTITUTION:The base potential of input transistors (TRs) Q1, Q2, Q3 and Q4 is of the same level with V1=V2. Thus, the base potential of the differential pair TRs Q5, Q6 where its emitter is used in common and each base is connected to the collector of the other TR is equal and an equal collector current flows to the differential pair TRs Q5, Q6. Thus, a V0 is the highest output level and a V0' is the lowest output level. When the level difference between the input signals V1 and V2 is maximized and the relation of V1<V2 exists, the base potential of the TRQ5 is smaller than that of the Q6 in the TRs Q5, Q6 where the potential is decreased by a value of VBE via the input TRs Q4, Q5, then the TRQ5 is turned off and the Q6 is turned on. Thus, the V0 is the lowest output level and the V0' is the highest output level.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to an amplifier for cascade connection in order to obtain high conversion accuracy in cascade type analog-to-digital converters.

(Prior Art) In a cascade-type analog-to-digital converter (hereinafter referred to as an A/D converter), the amplifier, which forms the main component along with the comparator, is connected in cascade, so the accuracy of the A/D converter is low. , has a large impact on performance such as conversion speed.

Figure 1 is a block diagram of an m-bit A/D converter using the cascade conversion method.
5ISIN is an analog signal, VREF is a reference voltage NC
+, Ct~C,, -, , Crn are comparators, Dl, D,
~Dm-, I Dm is the digital output signal, A,, A2
-Am-1 is an amplifier.

In the circuits of and, the analog signal SIN held by the S/H is used as the first input, and the full scale voltage (hereinafter VF
The most significant bit is determined by the comparator C1, which uses the 1/2 level of VREF (abbreviated as R) as the second input, and obtains a digital output signal. The operation of the input amplifier A is performed in parallel with the conversion operation of the comparator C1. The amplifier is V
A circuit with input/output characteristics of o=21vt v21,
The output is used as an analog input signal for comparator C2 and amplifier A2 that constitute the next stage, and comparator C'l' operates in the same way as amplifier A1. From comparator C2, a digital output signal of the third significant bit is generated. D2 obtains an analog input signal from amplifier A2 to the comparator and amplifier connected to the next stage. Hereinafter, the same operation is performed in the cascaded comparators and amplifiers up to m stages, and each comparator C,,C,,...
...The output of cm-1+cm is the digital output signal,'
, D, . . . Dm-1, Dm, and the conversion of the analog signal into an m-bit digital signal is completed.

Generally, in electrical circuits configured in cascade, it is conceivable that errors due to some cause may be transmitted when transmitting signals. The cascade type A/D converter is no exception, and has the disadvantage that amplification errors accumulate and are transmitted to subsequent stages because multiple stages of amplifiers are connected in cascade. Furthermore, as shown in Figure 1, when a fixed bias voltage is used as the reference voltage of the amplifier, errors in the input/output characteristics are likely to occur due to this, which overlaps with the aforementioned drawback of accumulated errors. The impact is huge. Below, l5SCC'83
THPM14.1:”An 8b 50ns Mon
olithic A/D Converter with
The presentation of Internal S/H'' will be specifically explained as an example.

Figure 2 is a circuit diagram of the amplifier used in this example, with Q
ls + h2 is the input transistor, Q131 Q1
0 is the output transistor, v, , v is the input signal, VC1
+VC2 is collector output, VO is output signal, R1,,R
, 2°R, 3, R, 4 is the output load resistance, R, 5 + R1
6 is an emitter resistor for gain control, vcc I vgg is a power supply voltage, and IEE'l +' IEE2 is a constant current source. This circuit consists of two transistors Q1. + Q12 is a differential type, and two transistors QCs each have a collector and an emitter in common.
r Due to the circuit configuration in which the bases of each of Q14 are connected via a resistor, the input signal level becomes V, = V,
Sometimes transistor Q1. .

Since the operating conditions of Q10 are the same, equal current flows and VCt=
Vc2, so Vo = Vct - VBg (q,
3) Obtain an output level for Vo, and when Vs>Vs,
Since the collector current of transistor Qo flows more than that of Q and t, VC+ < V (4, so V□ == v
The output level of c2VIE(Q,,) is V. Furthermore, when V<V2, the collector current of transistors Q and t becomes smaller than that of transistor Q12, and VCI
> Vct, so vo-V C1-VBE(Q,
3) An output level of vo is obtained, and the overall conversion function has the characteristic of Vo ``'' 2 l Vs v21. Because of this circuit configuration, in order to connect this amplifier with one signal output terminal in cascade to transmit signals to the next stage, it is necessary to input a reference voltage signal in addition to the analog signal. If you don't, it won't work.

In this way, when using a fixed reference voltage as the input of an amplifier, the dependence of these parameters, such as fluctuations in the power supply voltage, operating current, and variations in elements, has a large effect on the input/output characteristics, and this has a large effect on the output amplitude. Of these, it appears as low-level fluctuations. As a result, 1/2 level of the input range of the analog signal deviates from the reference voltage and voltage, and the deviation is further increased in the next stage. Therefore, the comparison operation by each comparator is exactly 1/2 VFS r 1/4
There is a drawback that it is not possible to determine VFS to 1/2'''VFS, resulting in an error in the A/D conversion operation.

(Objective of the Invention) In order to eliminate these drawbacks, the present invention enables positive-phase and negative-phase output, so that the positive-phase output signal is used as the analog input signal of the next stage, and the negative-phase output signal is used as the reference voltage input of the next stage. The present invention provides an amplifier having a circuit configuration having input/output characteristics that can be used as a signal.

(Structure and operation of the invention) The present invention will be explained in detail below with reference to the drawings.

FIG. 3 is a diagram explaining the input/output characteristics of the amplifier of the present invention, where OI vo is the output signal and VllV2 is the input signal.The input/output characteristics are expressed as Vυ-Alv+-v21 (A is the amplification factor). In other words, when the analog signal and the reference voltage are equal, V1 = V2, ■ o - maximum output level +
VO"" is the lowest output level, and when the level difference between 2 and v2 is maximum, VO=minimum output level and r vo-maximum output level.

FIG. 4 shows an embodiment of the present invention, and shows the circuit configuration of an amplifier having the input/output characteristics shown in FIG. ■,.

v2 is the input signal, Ql, Q2. Ql, Q4 are input transistors, Q, , Q are differential pair transistors, R81R,
is a resistor for controlling the gain, R2lR2 is an output resistor,
IIJ is a constant current source, VO+ vo + voo + V
oo is the output signal, Q7 is the constant current source transistor, Vc
cr VBB + VEE is the power supply voltage.

In this circuit, first, when V=V, the input transistors Q+, Q2 . The base potentials of Qs and Q4 are at the same level. For this reason, a differential pair of transistors Q5. The base potential of Q is strong, and equal collector currents flow through these differential pair transistors Qs+Q6. In addition, the input transistor pair Q and Q41 that constitute the differential type, and the human-powered transistor pair Q2 and Q
, the emitter resistor Rs, R4 is the input transistor Q
, Q2 are inserted on the , Q2 side, respectively, so the input transistors Q, , Q2 are turned off, and the input transistors Q8 . Q is turned on, and the entire IEE current flows through the resistor R1, and no current flows through the resistor R2. Therefore, vo
indicates the highest output level, and ■ indicates the lowest output level.

Next, when the level difference between the input signals V1 and V2 becomes maximum and V<V2, the base potential of the transistor Q5゜Q6, which is lowered by one stage of VBE via the input transistor Q3゜Q, becomes Q5 on the Q5 side. Since the base potential of the input transistor Q is higher, the entire current of the IEE flows through the resistor R7. Therefore, Vo becomes the lowest output level + VO becomes the highest output level. Further, in the case of 1, V, > V, based on the same idea, the input transistor Q is finally turned on, so Vo becomes the lowest output level and '4' becomes the highest output level.

As described above, in this amplifier, the levels at V and -V become dark values, and outputs that are completely complementary to Vo and Vo can be obtained. When these Vo and Vo are used as input signals for the next-stage amplifier in a cascade configuration, the level at Vo-■ (when V of the next-stage amplifier is -V2) becomes a threshold, and the same operation is repeated. Since VO and HA have complementary characteristics, even if the power supply voltage or operating current changes, it only affects the amplitude, and the high and low levels of VO + VO remain the same, resulting in the output signal Vo - Vo. Input signal■
The relationship between , and ■2 always remains the same. That is, the threshold value is constant, and amplifier characteristics that are independent of power supply voltage and operating current can be obtained. - At the same time, differential pair transistor Q3. Since the input signal to the next stage comparator is obtained from the collector of Q6, the analog and digital output signals can be provided at separate terminals. Therefore, it is possible to avoid the influence of the switching operation in the comparator from appearing on the amplification characteristics.

As explained above, the amplifier of the present invention has v6=AIVI
- V21 is the input/output function, and two analog output signals with completely complementary characteristics and -1 are configured so that a digital output signal can be obtained separately. By using this circuit in the amplifiers connected in cascade in a cascade type A/D converter, the signal transmission characteristics are unaffected by fluctuations in power supply voltage and operating current, resulting in highly accurate A/D conversion. A D converter can be easily realized.

[Brief explanation of drawings]

Figure 1 is a block diagram of a conventional cascade type A/D converter, Figure 2 is a block diagram of a conventional cascade type A/D converter.
The figure shows a circuit example of an amplifier used in a conventional cascade type A/D converter, FIG. 3 shows an input/output characteristic diagram of the amplifier of the present invention, and FIG. 84 shows an example of the circuit configuration of the amplifier of the present invention. S/H...sample/hold circuit, A1. A2-A
rn-+ -amplifier, c,',c2~cm-tl
cm"' comparator, Q+s r Q+21 Qt r
Q2 + Qs + Q4...Input transistor,'
QI31Q14...output transistor, R11+
Rlm + Rls, R14, R1, R4... Output resistance, &s, 'Rse, Rs, R4... Emitter resistance, IEEE + IEE2 rIEE... Constant current source 'i Q,, Q,... Difference dynamic pair transistor, Q
t... Constant current source transistor, S + SIN...
・Analog signal, VREF...Reference voltage, v, ,
v, ...input signal, Vo + Vo r Von
+ Voo - output signal, Dl, D, ~Dm-, l
Dm...Digital output signal, Vc,', vc
2...Collector output signal, vCC+VEE+V
BB ”・Power supply voltage, VFS -7 le x cool voltage. Patent applicant: Nippon Telegraph and Telephone Public Corporation agent Tsuneo Shiramizu and one other person

Claims (1)

[Claims] The collectors of two transistors with a common emitter are connected to the base of the other transistor to form a flip-flop circuit. Two differential pair circuits are connected to each collector load. The first transistor of one differential pair and the second transistor of the other differential pair are input transistors to which a common signal is applied, and the second transistor of the other differential pair and the first transistor of the other differential pair are input transistors to which a common signal is applied. The transistor is used as an input transistor to which a common reference voltage is applied, a circuit for the purpose of gain control is inserted on the emitter side of the first transistor, and two collectors are connected to each other, the first transistor and the second transistor. By connecting corresponding output resistors to the connection points, complementary output signals can be obtained from the two connection terminals, and output signals can also be taken out from the respective collectors of the two transistors of the flip-flop circuit. An amplifier characterized in that it is configured as follows.