JPH0786945A - Analog/digital converting circuit - Google Patents

Abstract

PURPOSE:To reduce a through current during an automatic zero-in period by respectively interposing serial resistors between the source of a P-MOSFET at a comparator part and a control power source and between the source of an N-MOSFET and a ground. CONSTITUTION:At the analog/digital(A/D) converting circuit, during the automatic zero-in period, the through current flows between the source of the P- MOSFET at the comparator part and the power source and between the source of the N-MOSFET and the ground. Current feedback is loaded by the voltage drop of respective serial resistors 51 and 52, and the enlarged component of the through current is reduced. On the other hand, since a voltage at stable time at the junction of a P-MOSFET 11 and an N-MOSFET 12 can be reduced to the 1/2 of a control power source VDD by equalizing the values of the serial resistors 51 and 52, the operation of the comparator is not made instable. Further, the through current is prevented from flowing by constituting a buffer inverter as a clocked inverter and turning it off at automatic zero-in time, and power consumption is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog / digital conversion circuit widely used in electronic circuits.

[0002]

2. Description of the Related Art FIG. 5 is a circuit diagram showing an example of a conventional analog-digital conversion circuit. The analog-digital conversion circuit shown in FIG. 5 is called an 8-bit parallel type and is connected in series between the reference voltage terminal V _R and the ground terminal.
1, 2-2, ... 2-256, a voltage dividing resistor section 2 composed of 256 voltage dividing resistors (corresponding to 8 bits), and one input terminal of each of the connecting points of these voltage dividing resistors in sequence. , The other input terminal is connected to the analog signal input terminal A, and is a comparator unit 1 including 255 comparators 1-1, 1-2, ... 1-255,
The buffer inverter unit 3 including 255 buffer inverters 3-1, 3-2, ... 3-255 sequentially connected to the comparators of the comparator unit 1 and the buffer inverters of the buffer inverter unit 3 It is composed of a connected encoder 4. Each comparator 1-1, 1-2, ... 1-255 of the comparator unit 1
Is a P MOSFET 11 and an N MOSFET 1 in which their source / drain and drain / source are connected in series between the control power supply terminal V _D and the ground terminal, respectively.
2 and these P MOSFET 11 and N MOSF
A capacitor 13 having one terminal connected to each gate of the ET 12, and a switch circuit 14 connected between the other terminal of the capacitor 13 and a connection point of each voltage dividing resistor of the voltage dividing resistor section 2, A switch circuit 15 connected between the other terminal of the capacitor 13 and the analog signal input terminal A, and one terminal of the capacitor 13 and the PMOS.
The switch circuit 16 is connected between the connection points of the FET 11 and the N MOSFET 12. Also,
Each buffer inverter 3 of the buffer inverter unit 3
1, 3-2, ... 3-255 are P-MOSFETs in which the source / drain and the drain / source are connected in series between the control power supply terminal V _D and the ground terminal.
31 and N MOSFET 32, and P
The gates of the MOSFET 31 and the N MOSFET 32 are PMOS FEs of the comparators of the comparator unit 1.
The PMOSFET 31 and the N MOSFET 32 are sequentially connected to the connection point of the T 11 and the N MOSFET 12.
The connection point of is connected to the encoder 4.

The operation of this analog-digital conversion circuit will be described with reference to FIG. FIG. 6 shows the on / off operation of the switch circuits 14, 15 and 16 of each comparator of the comparator section 1, and the switch circuits 14 and 16 are turned on and the switch circuit 15 is turned off at timing T ₁ (hereinafter referred to as an auto-zero period). At T ₂ (hereinafter referred to as a comparison period), the switch circuits 14 and 16 are turned off and the switch circuit 15 is turned on, and the auto zero period and the comparison period are repeated after the timing T ₃ . During the auto-zero period, when the switch circuits 14 and 16 of each comparator 1-1, 1-2, ... 1-255 are turned on and the switch circuit 15 is turned off, one terminal of the capacitor 13 of each of these comparators has a control power supply. The voltage V _DD of the terminal V _D is changed to PMOSFE
A voltage ½ V _DD that is divided in half by T11 and N MOSFET 12 is applied, and the voltage V _RR of the reference voltage terminal V _R is divided into 1/256 by each voltage dividing resistor to the other terminal. Voltages are applied sequentially and the capacitors 13 of each comparator are biased by these differential voltages. Next, in the comparison period, the switch circuits 14 and 1 of each comparator
6 is turned off, the switch circuit 15 is turned on, the bias voltage of the analog signal A _in and the comparators capacitor 13 which is input to the analog signal input terminal A is added in series, the analog signal A _in the comparator capacitor 1
When the bias voltage of 3 is exceeded, P MOSFET1
1 and the input voltage V _in to the gates of N MOSFET 12
Is input, the P MOSFET 11 is turned off, and the N MOSF
The ET 12 is turned on, and the output voltage V _out of the “L” signal is output from these connection points. These "L" signals are supplied to the buffer inverters 3-1, 3-2, ... 3-255.
Is converted into an “H” signal and input to the encoder 4.
The encoder 4 is each buffer inverter 3-1, 3-2,
Or ... 3-255 is "L" signal "H" to determine the magnitude of the analog signal A _in by either a signal, digital signal D of 8 bits from the digital signal output terminal D
Output _out .

[0004]

In the analog-to-digital conversion circuit described above, the capacitors of the comparators of the comparator section in the auto-zero period have the voltage of the reference voltage terminal divided by the voltage dividing resistor section and the voltage of the control power supply terminal. To PM
It is biased by the difference voltage of the voltage divided by 1/2 between the OSFET and the N MOSFET.
The states of the FET and the N MOSFET are as shown in FIG. In each of FIGS. 7A and 7B, the horizontal axis represents the gate input voltage V _in , and the vertical axis represents the PMOS (a).
Output voltage V _{out at} the connection point of FET and NMOSFET,
(B) shows the through current I flowing from the P MOSFET to the NMOSFET. In FIG. 7, in the initial state, the gate input voltage V _in is zero, the P MOSFET is on, and the N MOS is on.
Although the FET is off, the voltage obtained by dividing the voltage at the reference voltage terminal by the voltage dividing resistor is input to the gates of these P MOSFET and N MOSFET during the auto-zero period, so that this input voltage rises. N MOSF
ET starts to turn on, and as shown in FIG.
Flows. Then, when the output voltage V _out reaches half of the voltage V _{DD at} the control voltage terminal, it stabilizes, but at this time, the through current becomes maximum and the power consumption increases. Since this output voltage V _out is input to the buffer inverter, the P MOSFET and N
In the MOSFET as well, a through current flows and power consumption further increases.

An object of the present invention is to provide a PMOS for a comparator.
The through current of the FET and N MOSFET is reduced, and further, the P MOSFET and NM of the buffer inverter are reduced.
An object of the present invention is to provide a low power consumption analog-digital conversion circuit in which the through current of the OSFET is reduced.

[0006]

In order to achieve the above-mentioned object, the present invention provides a voltage dividing resistor section composed of a plurality of voltage dividing resistors connected in series between a reference voltage terminal and a ground terminal. One of the input terminals is sequentially connected to the connection point of each of these voltage dividing resistors, and the other input terminal is connected to the analog signal input terminal. Is an analog-digital conversion circuit composed of a buffer inverter unit composed of a buffer inverter and an encoder connected to each buffer inverter of the buffer inverter unit, wherein each comparator of the comparator unit has a control power supply terminal and P MOSFET and N MOSFET connected in series between ground terminals
And a capacitor whose one terminal is connected to each gate of these P MOSFET and N MOSFET,
A first switch circuit connected between the other terminal of this capacitor and the connection point of each voltage dividing resistor of the voltage dividing resistor section, and between the other terminal of this capacitor and the analog signal input terminal. A second switch circuit connected thereto, and a third switch circuit connected between one terminal of this capacitor and the connection point of the P MOSFET and the N MOSFET. A first series resistor is provided between the source of the P MOSFET and the control power supply terminal, and a second series resistor is provided between the source of the N MOSFET of each comparator and the ground terminal.
Connect the series resistance of each. Alternatively, the source of the P MOSFET of each comparator in the comparator section is connected, the first series resistor is connected between this connection point and the control power supply terminal, and the source of the N MOSFET of each comparator is connected, and this connection point and ground. A second series resistor is connected to the terminal. Then, in these analog-digital conversion circuits, the resistance values of the first series resistor and the second series resistor are made equal. Further, each buffer inverter of the buffer inverter section of these analog-digital conversion circuits is constituted by a locked buffer inverter.

[0007]

In the analog-digital conversion circuit of the present invention, the P-MOSFE of each comparator in the comparator section is
A first series resistor is connected between the source of T and the control power supply terminal, and a second series resistor is connected between the source of the N MOSFET and the ground terminal, or the P MOSFET of each comparator in the comparator section is connected. A source is connected, a first series resistor is connected between this connection point and the control power supply terminal, a source of the N MOSFET of each comparator is connected, and a second series resistor is connected between this connection point and the ground terminal. Since these are connected, these P MOSFET and N M
Current feedback is applied to the OSFET due to the voltage drop of the series resistance due to the through current flowing therethrough, the magnitude of this through current is reduced, and the power consumption is reduced. Also,
By making the resistance values of the first series resistor and the second series resistor equal, these P
Since the stable voltage at the connection point between the MOSFET and the N MOSFET can be set to 1/2 of the voltage at the control voltage terminal, the operation of the comparator does not become unstable. Furthermore, since each buffer inverter of the buffer inverter section is used as a clocked inverter and these buffer inverters are turned off during the auto-zero period, a through current is prevented from flowing in the P MOSFET and the N MOSFET of these buffer inverters, and power consumption is further reduced. Reduce.

[0008]

1 is a circuit diagram showing an embodiment of an analog-digital conversion circuit of the present invention. The analog-to-digital conversion circuit of the present invention shown in FIG. 1 is the same as the conventional analog-to-digital conversion circuit shown in FIG. 5 except that each of the comparators 1-1, 1-2, ...
Between the source of the FET 11 and the power supply terminal V _D , first series resistors 51-1, 51-2, ...
Second series resistors 52-1, 52-2, ..., 52-255 are respectively connected between the source of the MOSFET 12 and the ground terminal.

In this analog-to-digital conversion circuit, in the auto-zero period, the voltage obtained by dividing the voltage of the reference voltage terminal V _{R by} the voltage dividing resistor unit 2 is used as each comparator 1-1, 1-2 ,.
.. 1-255 P MOSFET 11 and N MO
Input to the gate of SFET12, N MOSFET1
When 2 starts the ON operation and a through current I flows, this through current flows through the first and second series resistors 51 and 52, so that a current drop occurs in the P MOSFET 11 and the N MOSFET 12 due to the voltage drop of these series resistors 51 and 52. Feedback is applied and the magnitude of this shoot-through current is reduced. This current feedback occurs because the drain current I _D (through current) of the MOSFETs 11 and 12 is proportional to the voltage between the gate and the source. Therefore, the resistance values of the series resistors 51 and 52 are expressed by the equation (1). Set to a range that satisfies.

[0010]

## EQU1 ## V _DD / 2 ≧ I _D · R ₅₂ + V _TH where V _{TH is} the threshold value of the MOSFET Further, by setting the resistance values of the series resistors 51 and 52 to be the same resistance value, P MOSFE in the auto-zero period.
Since the stable voltage at the connection point of T11 and N MOSFET 12 can be set to 1/2 of the voltage V _DD of the control power supply terminal V _D ,
The operation of the comparator does not become unstable.

In this way, the P M of each of the comparators 1-1, 1-2, ... 1-255 of the comparator unit 1 is
The through current flowing through the OSFET and the N MOSFET is reduced. Other operations are the same as those in FIG. FIG. 2 is a circuit diagram showing a different embodiment of the analog-digital conversion circuit of the present invention. FIG. 2 shows the comparators 1-1 and 1-1 of FIG.
The first and second series resistors 51 and 52 connected in series to the source of the P MOSFET 11 and the source of the N MOSFET 12, respectively 1-2, ...
Instead of the common series resistors 61 and 62, the sources of the P MOSFETs 11 of these comparators are connected, and the first series resistor 61 is connected between this connection point and the control power supply terminal V _D. N MOSF
The source of ET12 is connected, and the second series resistor 62 is connected between this connection point and the ground terminal.

The operation of this analog-digital conversion circuit is similar to that of FIG. 1, but the number of series resistors is reduced. Figure 3
4 and FIG. 4 are circuit diagrams showing further different embodiments of the analog-digital conversion circuit of the present invention. 3 and 4 respectively show buffer inverters 3-1, 3-2, ... Of the buffer inverter unit 3 of FIG. 1 or FIG.
3-215 is a clocked inverter 3A-1, 3A-
2, ... 3A-215. The clocked inverter is, for example, the PM of the buffer inverter 3-1, 3-2, ... 3-255 shown in FIG. 1 or 2.
P between the source of the OSFET 31 and the control power supply terminal V _D
The source / drain of the MOSFET 33 is an NMOS
N between the drain and source of the FET 32 and the ground terminal
The drain and the source of the MOSFET 34 are connected, and the gates of the P MOSFET 33 and the N MOSFET 34 are connected to the clock terminal C.

In the analog-digital conversion circuit shown in FIG. 1 or 2, the P-MOSFE of each of the comparators 1-1, 1-2, ... 1-255 in the auto-zero period.
The voltage at the connection point between T11 and N MOSFET 12 is 1/2 the voltage V _DD of the control power supply terminal V _D divided by 1/2.
It becomes V _DD , and this voltage is applied to each buffer inverter 3-1.
3-2, ... 3-255, since these are output to the gates of the P MOSFET 31 and N MOSFET 32, these P MOSFET 31 and N MOSFET 32
A through current flows through the clock signal C _{C in} FIG. 3 and FIG.
By P MOSFET31 and N MOSFE
P-MOS connected in series to the source of T32
The FET 33 and the N MOSFET 34 are turned on during the comparison period and turned off during the auto-zero period, so that the through current does not flow in the clocked buffer inverter except during the transition.

[0014]

In the analog-digital conversion circuit of the present invention, the through current of the comparator during the auto-zero period is reduced and the through current of the buffer inverter is eliminated, so that the power consumption is reduced. Further, due to the reduction in power consumption, the area of a chip formed as a semiconductor integrated circuit is reduced and the cost is reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of an analog-digital conversion circuit of the present invention.

FIG. 2 is a circuit diagram showing another embodiment of the analog-digital conversion circuit of the present invention.

FIG. 3 is a circuit diagram showing still another embodiment of the analog-digital conversion circuit of the present invention.

FIG. 4 is a circuit diagram showing still another embodiment of the analog-digital conversion circuit of the present invention.

FIG. 5 is a circuit diagram showing an example of a conventional analog-digital conversion circuit.

6 is a time chart showing the operation of the switch circuit of the comparator of FIG.

7 shows the operation of the comparator of FIG. 5, (a) showing P MOSFET and N MOSFE connected in series.
Input voltage-output voltage characteristic diagram of T, (b) Input voltage-through current characteristic diagram of P MOSFET and N MOSFET connected in series

[Explanation of symbols]

 1 Comparator part 1-1 Comparator 11 P MOSFET 12 N MOSFET 13 Capacitor 14 Switch circuit 15 Switch circuit 16 Switch circuit 2 Voltage dividing resistor part 2-1 Voltage dividing resistor 2-2 Voltage dividing resistor 3 Buffer inverter part 3-1 Buffer inverter 3A-1 Clocked buffer inverter 31 P MOSFET 32 N MOSFET 33 P MOSFET 34 N MOSFET 4 Encoder 51-1 First series resistance 52-1 Second series resistance 61 First series resistance 62 Second series resistance

Claims (4)

[Claims] 1. A voltage dividing resistor section composed of a plurality of voltage dividing resistors connected in series between a reference voltage terminal and a ground terminal, and one input terminal of each of the connecting points of these voltage dividing resistors in sequence. A comparator section that is connected and the other input terminal is connected to the analog signal input terminal, a buffer inverter section that is composed of a buffer inverter that is sequentially connected to each comparator of this comparator section, and a buffer inverter section of this buffer inverter section. An analog-digital conversion circuit including an encoder connected to each buffer inverter, wherein each comparator of the comparator section includes a P MOSFET and an N MOSFET connected in series between a control power supply terminal and a ground terminal,
A capacitor having one terminal connected to each gate of the P MOSFET and the N MOSFET, and a capacitor connected between the other terminal of the capacitor and each connection point of the voltage dividing resistors of the voltage dividing resistor section. No. 1 switch circuit, a second switch circuit connected between the other terminal of this capacitor and the analog signal input terminal, one terminal of this capacitor, and the P MOSFET and N.
A third switch circuit connected between the connection points of the MOSFETs, wherein a first series resistor is provided between the source of the PMOSFET of each comparator of the comparator section and the control power supply terminal. An analog-digital conversion circuit characterized in that a second series resistor is connected between the source of the N MOSFET and the ground terminal. 2. The circuit according to claim 1, wherein the sources of the P MOSFETs of the comparators of the comparator section are connected, and a first series resistor is connected between this connection point and the control power supply terminal. An analog-digital conversion circuit, characterized in that a source of a MOSFET is connected and a second series resistor is connected between this connection point and a ground terminal. 3. An analog-digital conversion circuit according to claim 1, wherein the resistance values of the first series resistor and the second series resistor are equal. 4. An analog-digital conversion circuit according to claim 1, wherein each buffer inverter of the buffer inverter section is a clocked inverter.