JPS60172822A - Digital phase synchronization circuit - Google Patents

Abstract

PURPOSE:To obtain a circuit following to an input signal with a high frequency and with very simple hardware constitution by constituting the converting table provided to a phase detecting circuit so that an input signal and a reference phase signal are inputted and the sinusidal value, cosine value of the reference phase signal and the input signals are multiplied and the result is converted outputted. CONSTITUTION:A phase detecting circuit 10 applies two input signals x=cosphi, y=sinphi orthogonal to each other by using a reference phase signal phi' and a phase error signal (e) with respect to the reference phase signal phi' is outputted. Two converting tables 13, 14 consisting of ROMs are provided to a phase detection circuit 10. The 1st conversion table 13 inputs the 1st input signal (x) and the reference phase signal phi' and outputs a converting value stored in an address decided by the (x) and phi'. Multipliers which had been required are eliminated with the very simple constitution where two each of 8-kbyte ROMs and exclusive OR circuit only are used.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a digital phase synchronization circuit constructed of digital circuits.

[Technical background of the invention]

In recent years, with the remarkable progress of semiconductor technology, various attempts have been made to digitize conventional analog circuits and construct highly reliable lines. In the field of communications, for example, phase synchronized circuits constructed from digital circuits have come to be used in modulators and demodulators for data communications using telephone lines.

For example, as shown in FIG. 1, such a digital phase synchronization circuit includes a phase detection circuit consisting of sine and cosine conversion tables 1 and 2 constructed of ROM or the like, a multiplier 3.4, and a synthesis circuit 5. It has a wave circuit 6. In this phase detection circuit 6, two input signals x having a mutually orthogonal phase relationship are
=A■φ* '/'''IFIφ and the sine of the reference phase signal φI fed back from the reference phase generation circuit 7.

Synthesize the product of cosine transformation value φ′ and residence φ′ and get 6 = A
+Jnφ tuft φ'-Acosφsinφ'= As1n
(φ−φ′) . . . (1) A phase error signal e is output. The phase error signal e is passed through a digital low-pass filter 8.
The harmonic components are removed by the reference phase generation circuit 7.
given to. The reference phase generating circuit 7 controls the phase of the reference phase signal φl so that the phase error signal e becomes zero.

[Problems with background technology]

The digital phase-locked circuit configured in this manner requires multipliers 3 and 4 for multiplying the input signal and the output signal of the conversion table 1.2, as shown in FIG.
Since multipliers generally have complex circuits, efforts have been made to reduce the number of multipliers as much as possible, such as by performing time-sharing processing.

However, as the frequency of the input signal to be handled becomes high, time division processing as described above becomes impossible, so in the end, the multiplier 3
．． 4 has no choice but to be dedicated. For this reason, there are problems in that the hardware configuration becomes complicated and power consumption also increases.

Furthermore, conventionally, when an overflow of digits occurs due to internal calculations, there has been a problem in that the phase error signal e fluctuates greatly, resulting in extremely large noise. In other words, as shown in Figure 2, if the input signal is a signal indicated by two points, if this input signal is subjected to phase rotation and moved to point Q, this input signal will be within the dynamic range (the dotted line in the figure). )
, the phase information is converted to a point Q', and the phase information becomes very different from the actual phase information. Therefore, conventionally, as shown in FIG. 3, a measure has been taken to limit the input signal by l/1/'T of the dynamic range to deal with the problem. For this reason, a limiter circuit must be added separately, which also poses the problem of complicating the hardware configuration.

[Purpose of the invention]

The present invention has been made in view of the above problems, and its object is to be able to follow high frequency input signals, and to have a hardware configuration. □Eng.□. , 1 Ka. The purpose of this invention is to provide a 42"2." synchronous circuit.

[Inplantation of invention]

The present invention provides a conversion table provided in a phase detection circuit,
It is characterized in that it receives an input signal and a reference phase (No. F7), and converts and outputs the product of the sine value and cosine value of the reference phase signal and the input signal.

That is, the sine and cosine conversion of the reference phase signal and the multiplication of phase detection are performed simultaneously using the conversion table.

〔Effect of the invention〕

According to the present invention, when an input signal and a reference phase signal are given to the conversion table, the conversion table directly converts and outputs the product of the sine and cosine values of the reference phase signal and the input signal, so the multiplier No longer needed. Moreover, since the above conversion table can be easily implemented in a ROM, the node configuration is extremely simple and power consumption can be reduced. Furthermore, since there is no need to perform time-division processing, it is possible to sufficiently follow high frequency input signals.

Furthermore, when using the above conversion table, if the conversion output value is set so as not to exceed a predetermined value, it is possible to add a limiter effect to the input signal without adding a special limiter circuit. can.

[Implementation sequence of the invention]

The details of the present invention will be explained below based on the illustrated embodiments.

FIG. 4 is a schematic diagram showing the configuration of a digital phase synchronization circuit according to an embodiment of the present invention.

In the figure, 10 indicates two input signals x=
This is a phase detection circuit that detects the phase of Yongφ, y−廀φ using a reference phase signal φ′ and simultaneously outputs a phase error signal e regarding the reference phase signal φ′. A digital low-pass filter 12 removes the error signal e/12 from the low-pass filter 11.
A reference phase generation circuit 12 which is controlled by the reference phase signal φ' and outputs the reference phase signal φ' is shown.

The phase detection circuit 10 includes two conversion tables J 3 , J 4 . is provided.

The first conversion table 13 receives the first input signal
′ = A cosφ ・Earth φ′ ・(1) is outputted as a converted value.

The second conversion table 14 receives an input signal y of $2 and a reference phase signal φ', and stores y' at an address determined by these y and φ': y'■φ' = A stnφ ・瓢φ' (2) It is used to output the converted value.

Therefore, the required capacity of the ROM constituting these conversion tables 13 and 14 is set as follows. Now input signals x, y and reference phase signal φ' are each 8
When configured with bits, the required capacity is 128 bytes (2 + 6 x 2). However, since it is necessary to reserve the most significant bit of the above Xr'l as a polarity pit and the upper two bits of the above φ' as a bit string representing a quadrant, the conversion value xl that can be requested.
The number of data representing the absolute value of y′ is actually 2×2=16 bytes. Therefore, it is conceivable to separately determine only the polarity bit and the quadrant bit to reduce the required ROM capacity.

That is, for example, in the case of the conversion table 13, the exclusive OR circuit 16 determines the bits that distinguish between the good quadrant and the good quadrant, and generates a sign bit indicating the polarity of Acosφ/picture φI. This is ROM 7 F is 8
Therefore, each conversion output signal x / y I of each conversion table 13, 14 is synthesized by the synthesis circuit 15 and e ``''X' + y' = A It is output as a phase error signal e (φ−φ′) (3). This signal e is turned into a signal e' with harmonic components suppressed by a low-pass filter 11, and is applied to a reference phase generation circuit 12. Thus, the phase of the reference phase signal φ' is controlled to follow the phase φ of the input signal to the reference phase generation circuit 12.

In this manner, the present embodiment has an extremely simple configuration in which only two 8-byte ROMs and two exclusive OR circuits are provided, thereby making it possible to eliminate the multiplier that was conventionally necessary. Moreover, in this case, there is no need to perform time-division processing, and the processing time is only the access time of the ROM, so that it is possible to handle extremely high frequency input signals.

Note that the present invention is not limited to the above embodiments,
For example, a carrier tracker used in a polyphase digital phase keying (PSK) demodulator.

It can also be applied to King circuits, etc.

FIG. 6 shows one embodiment of this, in which the phase detection circuit 20
4 conversion tables 21. tx.

23.24 and the above conversion table 21. :l:j and each of the conversion outputs of the conversion table 22.240 above are combined. In addition, a third combining circuit 27 is provided which inputs both outputs of the second combining circuits 25 and 26 and outputs a phase error signal e.

Therefore, the above conversion tables 21 and 22 both assume that the modulation input 4g' Part φ
・S stone φ'...(5) Outputs the variable m value. On the other hand, the above conversion table 23724 both uses the modulated input signal y
= A sloφ and reference phase signal φ′ are input, respectively y + ”= A sloφ ・l11n
φ' − ((i) y'2 = A sinφ'Ql11φ
'...(7) Output the converted values @ Then, these converted values X, and )'l, X2 and y
2 is the first. Arithmetic processing is performed by the second synthesis circuit 25゜26, and x' = x, +y, = A focus (φ-φ')...
・(8) y'=y2-x2=As1t+(φ-φ')
- The orthogonal demodulation output is expressed as (9).

Note that the third synthesis circuit 27 is for providing the phase detection circuit 20 with the same number of stable points as the number of phases.For example, in the case of two-phase PSK, X' at both the stable points of 0 and π Since the polarities of y′ are different, the polarity of y′ is switched according to the polarity of
8 to the reference phase generation circuit 29. Specifically, this third synthesis circuit 27 is a two-phase PSK
In this case, an exclusive OR circuit or a circuit that generates a phase error signal by switching the polarity of the output signal of the second combining circuit 26 depending on the polarity of the output signal of the first combining circuit 25 can be considered. In addition, in the case of 4-phase PSK, the first combining circuit 25
and the polarity of the output signal of the second combining circuit 26,
If you switch the polarities of the output signals of the other side that are orthogonal to each other and take the difference between the two signals, the phase error for 4-phase PSK /it is L.
-1 tto d) -to 1mtjJam 4L
I; 5mMJ'nj61+ may be obtained. In this way, the third
The synthesis circuit 27 can be modified in various ways both for PSK signals having the same number of phases and for the number of PSK modulation phases.

As described above, by applying the present invention to a multiphase PSK carrier tracking circuit, a carrier tracking circuit that conventionally required a large number of multipliers and units can be realized with an extremely simple configuration. It has a great effect.

[Brief explanation of drawings]

Figure 1 is a diagram showing the schematic configuration of a conventional digital phase-locked circuit, Figure 2 is an explanatory diagram showing the influence of internal calculation overflow of an input signal in a conventional phase detection circuit, and Figure 3 is a diagram showing the circuit. An explanatory diagram showing an input signal when limiting and limiting effects are added, FIG. 4 is a block diagram showing a schematic configuration of a digital phase synchronization circuit according to an embodiment of the present invention,
FIG. m5 is a professional diagram showing the configuration of the conversion table section in the same circuit, and FIG. 6 is a block diagram showing the schematic configuration of a digital phase synchronization circuit according to another embodiment of the present invention. 1#2.13.14.21-24...conversion table,
3.4... Multiplier, 5, 15, 25. 26... Synthesizing circuit, 6.10.20... Phase detection circuit, 7, 12.
29...Reference phase generation circuit, 8.11.28...Digital low-pass filter.

Claims (9)

[Claims] (1) A first conversion table that receives a first input signal and a reference phase signal and outputs the product of the sine value of the first input signal and the reference phase signal; a second conversion table which inputs a second input signal having a quadrature phase and the reference phase signal and outputs the product of the second input signal and the cosine value of the reference phase signal; . a synthesizing circuit that synthesizes the outputs of the second conversion table to generate a phase error signal of the reference phase signal for the first and second input signals; and a low-frequency synthesizer that removes harmonic components of the phase error signal. A digital phase synchronization circuit comprising: a pass filter; and a reference phase generation circuit that is controlled by the output of the low pass filter and generates the reference phase signal. (2) The conversion table is an RO that outputs the absolute value information of the product.
2. The digital phase synchronization circuit according to claim 1, further comprising a logic circuit that outputs code information of the product. (3) The digital phase synchronization circuit according to claim 1, wherein the conversion table has a limiting function for input signals. (4) a first conversion cheatle that receives a first input signal and a reference phase signal and outputs a product of a cosine value of the first input signal and the reference phase signal; a second conversion table that receives the phase signal as an input and outputs the product of the first input signal and the sine value of the reference phase signal;
a third conversion table that outputs the product of the sine value of the second input signal and the reference phase signal, which is in direct phase with respect to the input signal; and the product of the cosine value of the second input signal and the reference phase signal; a fourth conversion table that outputs, a first synthesis circuit that synthesizes the outputs of the first and third conversion tables, and a second synthesis circuit that synthesizes the outputs of the second and fourth conversion tables; a third combining circuit that combines the outputs of the first and second combining circuits to generate a phase error signal of the reference phase signal with respect to the first and second input signals; a low-pass filter that removes wave components;
A digital phase synchronization circuit comprising: a reference phase generating circuit that generates the reference phase signal under control by the output of the low-pass filter. (5) The conversion table is an RO that outputs the absolute value information of the product.
5. The digital phase detection circuit according to claim 4, comprising: M and a logic circuit that outputs sign information of the product. (6) The digital phase synchronization circuit according to claim 4, wherein the conversion table has a limiting function for input signals. (7) The digital phase synchronization circuit according to claim 4, wherein the third synthesis circuit is an exclusive OR circuit which inputs the six output signals of the first and second synthesis circuits. (8) The third combining circuit generates a phase error signal by switching the polarity of the output signal of the second combining circuit depending on the polarity of the output signal of the first combining circuit. 4. Digital phase synchronization circuit according to item 4. (9) The third combining circuit outputs a first error signal obtained by switching the polarity of the second combining circuit depending on the polarity of the output signal of the first combining circuit, and a polarity of the output signal of the second combining circuit. The second error signal obtained by switching the polarity of the first synthesis circuit and the first and second error signals are synthesized to generate a phase error signal. Digital phase synchronized circuit.