JPS6017183B2 - Digital data signal conversion circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital data signal conversion circuit that converts a digital data signal having a small number of bits and changing roughly into a digital data signal having a large number of bits and changing smoothly.

Generally, it is desirable to reduce the number of bits in a digital data signal. The reason is as follows. That is, in order to transmit a digital data signal with a large number of bits, a large number of wiring lines are generally required and the configuration becomes complicated. Furthermore, when a circuit that generates or processes a digital data signal with a large number of bits is constructed using an IC or the like, it is naturally necessary to have a large number of pins. As is well known, the price of IC etc. increases as the number of bins increases. Therefore, a circuit that handles digital data signals with a large number of bits has a complicated structure and is expensive. but,
The fact that the number of bits in the digital data signal is small means that
It has the disadvantage that the data is coarse and its accuracy is low.

For example, a touch response detection circuit installed in the keyboard of a digital electronic musical instrument (detects key pressing speed, key pressing pressure, lateral movement of keys, etc., and uses this data to control the musical sounds generated). When controlling the timbre of a generated musical sound using an output circuit (output circuit), or when controlling the volume of a generated musical sound using an expression pedal of a digital electronic musical instrument, a high-precision digital data signal with a large number of bits is normally used. However, since the number of bits of the digital data signal is small, the timbre and volume changes are step-like. The present invention aims to compensate for the drawbacks of the above-mentioned conventional system, and provides a digital data signal conversion circuit that converts a digital data signal with a small number of bits into a corresponding digital data signal with a large number of bits. be. The digital data signal conversion circuit of the present invention includes an up/down counter that outputs a count value with a number of bits greater than the number of bits of an input digital data signal, and a clock pulse for counting when the up/down counter exceeds the number of bits. It consists of an oscillator and a comparator that compares the magnitude relationship between the input digital data signal and some upper bits of the count output from the up/down counter.

According to the digital data signal conversion circuit of the present invention, the counting operation stop, count up operation, and count down operation of the up/down counter are controlled according to the output of the above comparator, thereby controlling the up/down counter.
The count value of the down counter is made to interpolate the input digital data signal sequentially, and the count value of the up/down counter is output as a new converted digital data signal. The present invention will be further described in detail below with reference to embodiments shown in the accompanying drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention,
A 5-bit input digital data signal OD is input to the first input terminal A of the comparator 1, and the second input terminal B
A data signal N〇 of the upper 5 bits of the 10-bit converted digital data signal ND (count value of the counter 3) outputted from the up/down counter 3 is inputted to the input circuit.

Comparator 1 compares the magnitude of data signal OD input to input terminal A and data signal N〇 input to input terminal B,
In the case of OD〉N〇, the logical value "
1”, and if OD<N〇, the first output terminal 0
1 to output a logic value "0", and outputs a logic value "1" from the second output terminal 02 only when OD=ND'. The first output terminal 01 of the comparator 1 is the up/down designation input terminal U of the up/down counter 3.
/D, and the second output terminal 02 is connected to the count stop command input terminal CS. A clock pulse J output from an oscillator 5 is input to a counting input terminal Ci of the up/down counter 3. The up/down counter 3 outputs a logical value " to the count stop command input terminal CS.
When 1" is input, the counting operation is stopped. Also,
If a logical value “0” is input to the count stop command input terminal CS and a logical value “0” is input to the up/down designation input terminal U/D, the up/down counter 3 is in the up mode. - is set to count input terminal C
Sequentially count up the clock pulses ◇ input to i. In addition, if a logical value "0" is input to the count stop command input terminal CS and a logical value "0" is input to the up/down designation input terminal U/D, the up/down counter 3 is the clock pulse that is set to down mode and input to the counting input terminal Ci◇
count down sequentially. This up/down counter 3 outputs its counted value as a 10-bit data signal ND, and as described above, the data signal N〇 of the upper 5 bits of this data signal ND is input to the input terminal B of the comparator 1. There is. Furthermore, the clock pulse output from oscillator 5? The oscillation frequency of the digital data signal OD is assumed to be sufficiently higher than the change frequency of the digital data signal OD. The operation of the digital data conversion circuit of the present invention having the above configuration will be described next.

(Data signal OD) > (Data signal N〇) In this case, a logical value “1” is output from the first output terminal 01 of the comparator 1, and a logical value “1” is output from the second output terminal 02. “
0” is output.

Therefore, a logic value "0" is input to the count stop command terminal CS of the up/down counter 3, and a logic value "1" is input to the up/down designation input terminal U/D. Therefore, the up/down counter 3 is set to the up mode. Therefore, the up/down counter 3 sequentially counts up the clock pulse 0 inputted to its counting input terminal Ci, and increases its count value sequentially. The up/down counter 3 outputs this count value as a 10-bit converted digital data signal ND, and as described above, the upper 5 bits of the data signal N〇 are input to the second input terminal B of the comparator 1. Ru. This data signal ND' also gradually increases in value as the up/down counter 3 counts up, and eventually reaches a value equal to the input digital data signal OD. At this time, the comparator 1 outputs the logical value "1" from the output terminal 02, and the up/down counter 3 outputs the logical value "1" from the count stop command terminal CS.
to temporarily stop the receiving and counting operation. A specific example of this case is shown in FIG. 2A.

Now, at time tl, the input digital signal OD becomes the binary value "01".
Suppose it is 10 bis.

In this case, the up/down counter 3 performs a count-up operation as shown in FIG. 2A, and the converted digital data signal ND gradually increases in value accordingly. Eventually, at time t2, the converted digital data signal ND
The data signal N〇 of the upper 5 bits of is the binary value “01100
'', the up/down counter 3 temporarily stops its counting operation. In this way, the converted digital data signal ND increases step by step in accordance with the clock pulses output from the oscillator 5, as shown in FIG. .That is,
If (data signal OD)>(data signal N〇),
A converted digital data signal N〇 is formed by multiplying the value of the input digital data signal OD.

This allows the 5-bit input digital data signal O
From D, a corresponding new converted digital data signal ND of 10 bits is formed. 'o- (Data signal OD) = (Data signal ND') In this case,
Comparator 1 outputs the logical value “1” from output terminal 02 as described above.
-up/down counter 3 outputs this logical value "
1" is received at the count stop command terminal CS, and the counting operation is temporarily stopped.

This state continues until the value of the input digital data signal OD changes next time. A specific example of this case will be explained using FIG. 2A.

As mentioned above, at time t2, the input digital data signal OD
When the value of the data signal N0 of the upper five bits of the converted digital data signal ND reaches the same value (01100''), the counting operation of the up/down counter 3 is temporarily stopped. At time t3, the input digital data signal O
When the value of D changes to the binary value "0110r", (data signal OD)>(data signal ND'), the up/down counter 3 again performs a count-up operation in the same way as in the case of 'I'. The converted digital data signal ND changes to follow the input digital data signal OD. In this state, at time t4, the data signal N〇 of the upper 5 bits of the converted digital data signal ND becomes the binary value "011".
It continues until it reaches 0r.

(Data signal OD) < (Data signal N〇) In this case, the comparator 1 outputs the logic value “0” from the output terminal 01.
” and a logic value “0” is output from the output terminal 02.

As a result, the up/down designation input terminal U/D of the up/down counter 3 and the count stop command input terminal C
Since the logical value "0" is input to S, the up/down counter 3 is set to the down mode. Therefore,
The up/down counter 3 sequentially counts down the clock pulses ◇ inputted to the counting input terminal Ci.
This count value is input to the input terminal B of the comparator 1 as the data signal ND' of the upper five bits of the converted digital data signal ND. Therefore, also in this case (data signal O
The up/down counter 3 counts down the clock pulse ◇ until D)=(data signal N〇).
This allows the 5-bit input digital data signal O
A corresponding 10-bit converted digital data signal ND is output from D. A specific example of this case will be explained using FIG. 2A.

When the input digital data signal OD changes from the binary value "01101" to "01011" at time t5, the up/down counter 3 performs a countdown operation, and accordingly, the converted digital data signal ND gradually becomes a smaller value. Eventually, at time t6, when the data signal N0 of the upper five bits of the converted digital data signal ND becomes the binary value "01011", the up/down counter 3 temporarily stops its counting operation. Furthermore, when the value of the input digital data signal OD changes at time t7, the counter 3 operates again in response to this change, and the converted digital data signal ND follows the value of the input digital data signal OD. As is clear from the above description, according to the above embodiment, it is possible to form a corresponding multi-bit (10-bit) converted digital data signal ND from a small-bit (5-bit) input digital data signal OD. can. In the specific example shown in FIG.
In the case of a signal that changes by a value of ``0000r'',
By appropriately setting the generation period of the clock pulse ◇ output by the oscillator 5, the input digital data signal OD
It is possible to obtain a converted digital data signal ND that is completely straight between discontinuous points. FIG. 3 shows an example in which the digital data signal conversion circuit of the present invention is applied to an electronic musical instrument.

The touch response detection circuit 11 has a function of detecting the key pressing speed, key pressing pressure, movement of the key after the key pressing, etc. on the keyboard of the electronic musical instrument, and outputting an analog detection signal TRS. ing. This touch response detection circuit 11 uses, for example, a piezoelectric element, conductive rubber, or the like. This detection signal (analog signal) TRS is input to an analog-to-digital converter (hereinafter referred to as an A/D converter) 12, and is converted into a relatively small-bit digital data signal OD. This digital data signal OD is input to the digital data signal conversion circuit 13 of the present invention and is converted into a new smoothly changing digital data signal ND having a large number of bits. This converted digital data signal ND
is input to the usage circuit 14 of the electronic musical instrument, and is used as a signal for controlling generated musical tones. Therefore, an electronic musical instrument using this digital data signal conversion circuit has a very smooth timbre and volume change, and does not have a stepped change in timbre or volume unlike conventional electronic musical instruments.

Therefore, its performance is significantly improved. In addition, in the application example of the present invention described above, the touch response detection circuit 11
directly outputs the digital data signal OD as the detection signal TRS.
When outputting , the A/D converter 12 becomes unnecessary. As is clear from the above description, according to the present invention, it is possible to obtain a converted digital data signal that changes smoothly with many bits from a digital data signal that changes coarsely with a small number of bits, and it is possible to interpolate a digital data signal with low precision. can be converted into highly accurate digital data signals.

Further, according to the present invention, rapidly changing input digital data is converted into slowly changing digital data, thereby making it possible to effectively remove noise and the like.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of this invention, FIGS. 2A and B are waveform diagrams explaining the operation of the embodiment shown in FIG. 1, and FIG. 3 shows one application example of this invention. It is a block diagram. 1... Comparator, 3... Up/down counter, 5... Oscillator, 11... Touch response detection circuit, 12... A/D converter ,
13... Digital data signal conversion circuit, 14...
...Circuit used. Figure 1 Figure 2 Figure 2 Figure 3

Claims (1)

[Claims] 1. an oscillator 5 that generates a clock pulse φ having a higher frequency than the change frequency of the input digital data signal OD;
An up/down counter 3 which outputs a count value with a number of bits greater than the number of bits of the input digital data signal and performs a counting operation in response to the above clock pulse; a comparator 1 for comparing the magnitude relationship between the input digital data signal and a signal ND' having the same number of bits, starting from the higher order of the count values output from the up/down counter;
When the comparison result in the comparator is OD>ND', the up/down counter is started to count up, when OD=ND', the up/down counter is stopped, and when OD<ND', the up/down counter is started to count up. - A digital data signal that controls a down counter to perform a countdown operation so that the count value of the up/down counter interpolates the digital data signal OD, and outputs this count value as a converted digital data signal. conversion circuit.