JPS60171737A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To contrive to flatten the surface of a semiconductor device by a method wherein the inside walls of grooves are formed by etching to have completely vertical surfaces in a substrate, and generation of V-shaped recess parts on the top surfaces of silicon to be epitaxially grown selectively and SiO2 layers to be obtained by oxidizing the silicon thereof is checked according to the above-mentioned process. CONSTITUTION:Dry etching is performed according to the RIE method using a first Si3N4 film 13 as a mask to form grooves 14 as shown in the figure B. Then after the inside surfaces of the grooves 14 are oxidizing to form SiO2 films 16 as shown in the figure C, an Si3N4 film is deposited according to the CVD method again to form a second Si3N4 film 17 on the whole surface. Moreover, an SiO2 film 18 is formed on the whole surface according to the CVD method as shown in the figure D in succession thereto. When the SiO2 film thereof is etched again according to the RIE method, the SiO2 films 18, the second Si3N4 films 17 and the SiO films 16 on the bases of the grooves 14 are etched to be removed wholly as shown in the figure E, and silicon is exposed at the bases in the grooves 14. At this time, when the etching condition is so as to make SiO2 and Si3N4 to have the same etching ratio, the inside surfaces of the grooves 14 completed with etching are formed to the vertical surfaces.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a method for manufacturing a semiconductor device suitable for high integration, particularly a semiconductor device having a trench-hole structure.

[Background technology]

Conventionally, field oxide films made by selective oxidation (LOCO8 method) have been used for isolation between elements in semiconductor devices such as ICs and LSIs, but with the recent demand for higher integration, groove-type isolation structures have become more popular. It has been proposed. As an example of this groove type isolation iron, the inventors proposed the following method on page 531 of the Proceedings of the 30th Applied Physics Association Conference, published in April 1983. That is, as shown in FIG. 1, grooves 2 are formed on the surface of a silicon substrate 10, silicon is selectively grown in the grooves 2, and this silicon is oxidized to form an SiO layer 3, thereby forming an isoconductive layer. It is to be used as a regiron. Usually, the groove 2 is formed by the first Si, N4 film 4.
A J 2 S Is N4 film 5 is formed in order to selectively oxidize only the silicon grown in the groove 2.

However, when the groove type isolation produced by this manufacturing method was further examined in detail, it was found that the following problems occurred. That is, the above-mentioned 11+, I
A groove 2 having a vertical inner wall is formed in a silicon substrate 1 by the E method.
However, if a (100) silicon crystal is used, a (111) plane 6 inclined at an angle of about 54° will appear at the top of the groove 2 due to the crystallinity (plane orientation) of the silicon, and a completely vertical inner plane will appear. It becomes difficult to form a wall shape.

For this reason, the growth on both sides of the silicon 3a (indicated by phantom lines in the figure) that is selectively grown epitaxially within the trench 2 is delayed, and facets 7 are formed on both sides of the upper surface of the silicon 3a. SiO.

Facets, that is, V-shaped recesses 7, are formed on both sides of the upper surface of the layer 3 between the layer 3 and the upper surface of the silicon substrate 1.

Therefore, the flatness of the silicon substrate 1 as a whole is impaired by the V-shaped recess 7 generated in this way, and when forming elements in a later process, for example, electrode material is buried in the recess 7, resulting in a short circuit. occurs. In addition, due to the presence of the inclined surface 4 in the upper part of the groove 2, stress tends to be concentrated in the vicinity of the inclined surface 6 during oxidation expansion of the epitaxially grown silicon 3a, causing crystal defects in the silicon ice plate 1. There is also.

In the RIE method, attempts have been made to reduce the degree of vacuum and change the etching conditions, such as increasing the power, to suppress the occurrence of the above-mentioned inclined surface, but it has not been possible to obtain a completely vertical surface, and the plasma It is also unfavorable from the point of view of damage.

[Purpose of the invention]

The object of the present invention is to form the inner wall of the groove into a perfectly vertical surface by etching, thereby selectively epitaxially growing silicon and oxidizing it to form a Si! It is an object of the present invention to provide a method for manufacturing a semiconductor device that can prevent the formation of a V-shaped recess on the upper surface of a layer to achieve planarization, and can also prevent the formation of crystal defects in a silicon substrate.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, following the formation of the 28th i3N4 film, an amorphous film of a required thickness is formed and the amorphous film and the 2nd Si3N film are formed.
By etching these two films by the RIE method under conditions where the etching ratio of the four films is the same, and performing selective oxidation in the following selective growth 9, isolation is formed.
It is possible to prevent the occurrence of V-shaped recesses in isolation and achieve planarization, and also to prevent the occurrence of crystal defects in a semiconductor substrate such as silicon.

〔Example〕

Figures 2-0 are diagrams showing the manufacturing process of the method of the present invention,
The steps will be explained below in order.

First, as shown in FIG. 2(a), the main surface of a silicon semiconductor substrate 11 with a (100) plane orientation is oxidized to form a thin SiO film 12, and then a first Si, N4 film 13 is formed by CVD or the like. Then, using a conventional photolithography technique using this as a photoresist, only the isolation forming region is opened. Next, this 18i3N4 film 13
Using this as a mask, dry etching is performed by the RIE method to form grooves 14 as shown in FIG. At this time, due to the crystallinity of the silicon substrate 1.1, (11
1) The surface is exposed, resulting in an inclined surface portion 15 having an angle of θ=approximately 54.7°.

Next, as shown in FIG. 00, the inner surface of the groove 1 film is oxidized to -S i
o. After forming the film 16, Si,
N4 dyN') '7 W:/Si, No. zSi
An sNa film 17 is formed on the entire surface. Furthermore, following this, a film 18 of Sin is formed on the entire surface by the CVD method as shown by ◎ in the same figure.

In this case, in order to improve the adhesion shape of the Sin film 18,
The CVD method is preferably carried out under high temperature and low pressure conditions. This SiO film 18 is formed as an amorphous film under the above-mentioned CVD conditions, and its thickness is sufficient to satisfy the conditions described later.

Then, if this is etched again by the RIE method, the Si0 on the bottom surface of the groove 14 is etched as shown in FIG.
2 membranes 18. 2nd Si, N, film 17 and Sin.

The entire film 16 is removed by etching, and silicon is exposed on the inner bottom surface of the trench 14. At this time, the etching conditions are S
It is important to set the etching ratio of iO2, Si, and N to be the same.
, and the fact that the film 18 is amorphous, the etched groove 14 has a vertical inner surface. At this time, S io and film 18 are also formed on the silicon substrate 11.
The second Si, N4 film 17 is etched, and the first Si, N4 film 17 is etched.
The N film 13 is exposed on the surface (the second SilN film 13 is also slightly etched and becomes thinner).

Next, as shown in FIG.
Lf, - selective epitaxial growth of silicon on silicon to selectively epitaxially grow silicon 1 in trench 14;
9 to approximately half the depth of the groove 14. At this time, since the inner surface of the groove 14 is vertical, the upper surface of the epitaxial silicon 19 is almost flat, and 77 sets are not generated on both sides of the upper surface.

Therefore, the epitaxial silicon 19 is oxidized to form a layer 20 in the groove 14 as shown in FIG.
If the 6 films on the surface of the substrate are then removed, even if the isolation is completed, a figure 7-shaped recess will not be formed on both sides of the top surface of the SiO layer 20, and the entire substrate can be planarized. can.

Furthermore, even if the oxidation progresses downward at this time, since the inner surface of the groove 14 is vertical and the width dimension is constant, the stress will not increase particularly in the lower part of the groove, and the crystal defects within the silicon substrate 11 will not increase. Occurrence can be prevented.

Here, the first Si3N4 film 13 and amorphous Sin.

Consider the thickness of each of the membranes 18. Now, as shown in FIG. 3, an amorphous SiO film 18. Second Si3N4 film 17. First Si, N, film 13 and Siot film 12 (
Let the film thicknesses of lf9 be a, b, c, and d, and the inclined surface portion 1
Let the height of 5 be e. θ is the inclination angle of the inclined surface portion 15 as described above.

In this case, in the etching by the RIE method shown in FIG.
1 must be prevented from being exposed. If it is exposed on the side surface, epitaxial growth will occur from there in the next step, and the above-mentioned effective epitaxial growth will be inhibited.

To satisfy this condition, amorphous 5i than the illustrated dimension
It is necessary to increase the thickness a of the n2 film 18, and xsta
Since nθ=e, a≧e/tanθ・・・・・・・・・・・・・・・
(1) is derived.

On the other hand, in order for the inner surface of the groove 14 to be a completely vertical surface, one dimension in the figure (the height of the two ends of the inclined surface of the amorphous %5i02 film 18) must be completely etched. At this time, considering the next process, the first Si3N on the surface of the substrate 11
, it is undesirable for the film 13 to be etched away.

Therefore, if the thickness of the first Si, N, film 13 to be left after etching is 2, then the condition a + b + c -z '> Y is required, and from this, c) 'y - (a + b) +z is derived. Here, one dimension is the angle ψ3. Since ψ are equal, y=e+f.

Confronted, eventually ・・・・・・・・・・・・・・・(2) is observed.

As described above, the amorphous S io, the thickness a of the film 18 and the first
The thickness C of the Si3N4 film 13 is the above (1), (2+
If the following conditions are met, a good groove can be completed.

〔effect〕

(1) Before etching the grooves by RIE method, the second Si
3N, a sufficiently thick amorphous SIO film is formed on the film, and RIE etching is performed on these SIO films.

Since the film and the second Si, N, film are etched under the same etching ratio conditions, the inner surfaces of the grooves can be formed into perfectly vertical surfaces.

(2) Since the inner surface of the groove can be made vertical, the oxidation of the silicon inside the groove can proceed uniformly, and the S
In this case, uneven stress is not generated in the layer, and crystal defects are not generated in the silicon substrate.

(3) Since the inner surface of the groove can be made a vertical surface, the top surface of the epitaxially grown silicon and oxidized Si layer can be flattened, and the formation of a figure 7-shaped recess on both sides of the top surface can be prevented, thereby flattening the substrate. can be achieved.

(4) In addition to conventional manufacturing methods, the inner surface of the groove can be etched vertically by simply forming an amorphous SiO2 film.
A good isolation structure can be obtained without increasing the number of steps.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Mona ℃・. For example, amorphous S
Other amorphous materials may be used in place of io. Furthermore, various conventionally known methods can be used for selective epitaxial growth and oxidation.

[Application field]

In the above explanation, the invention made by the present inventor was mainly applied to the technology for forming groove type isolation of semiconductor devices, which is the field of application that formed the background of the invention, but it is not limited to this. It can be applied to all semiconductor devices that require grooves or steps with steep sidewalls.

[Brief explanation of the drawing]

Fig. 1 is a cross-sectional view to explain the defects in the conventional method, Fig. 2 (A) to 0 are cross-sectional views showing the manufacturing method of the present invention in the order of steps, and Fig. 3 is a cross-sectional view to explain the method of calculating the film thickness. FIG. 11...Silicon substrate, 12...Siot film, 1
3... First Si3N4 film, 14... Groove, 15...
Inclined surface portion, 16... SiO, film, 17... 2nd S
i, N, film, 18... amorphous SiO*[, 19...
Ebitaxia/L/(growth) silicon, 20...Si
n, layer; Figure 1 Figure 3

Claims (1)

[Claims] 1. Steps of etching a groove on a semiconductor substrate using the first Si3N4 film as a mask; and forming a second Si3N4 film and an amorphous film to a sufficient thickness on the upper surface of the substrate or the inner surface of the groove. , a step of etching these second Si, N4 films, amorphous films, etc. by the RIE method at the same etching ratio, a step of selectively epitaxially growing a semiconductor in the groove, and a step of oxidizing this semiconductor to form the above-mentioned etching layer. 1. A method for manufacturing a semiconductor device 1, comprising the step of filling a trench with an oxide layer to provide isolation. 2. The amorphous film is Si formed by high temperature and low pressure CVD method.
o. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is a film. 3. The semiconductor device according to claim 1 or 2, wherein the amorphous film is formed to have a thickness greater than the thickness calculated from a predetermined relational expression so that the semiconductor cannot be exposed on the side surface of the groove. Production method.