JPS60170969A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To simplify the process of a device with its emitter provided with series- resistor by a method wherein an N-layer on a P-type Si substrate is coated with poly Si and an N-type oxide layer is laminated before heattreatment while a poly Si resisting film is simultaneously formed on an electrode leading film and an insulating film. CONSTITUTION:An opening is made on an SiO2 film 5a on a P-base 5 and an N-emitter 7 on the surface of an Si substrate and then a poly Si11 and BSG13 are laminated thereon to be left selectively on the upper part of the opening. Firstly overall surface is laminated with the PSG13 to be heattreated for diffusing in the poly Si11 and then a P<+> layer 11a and an N<-> layer 11b are formed to be selectively etched for leaving respectively on corresponding electrode windows and then leaving an N-layer 11c on the SiO2 film 5a to form a thin P<+> layer 5c on a P-base 5 coming into contact with the P<+> layer 11a. Secondly overall surface is coated with Al to be photoetched forming a connecting layer 12c, a base electrode 12B, an emitter electorde 12E and a wiring pattern of the emitter 7 and the resistance layer 11c. In such a constitution, the reliability of a semiconductor device may be improved since the processes of oxidation, impurity introduction and photoetching are reduced to shorten the production process making electrode leading process easier.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and is particularly used for manufacturing a semiconductor device IM having a crystal output and a resistor in series with an emitter.

[Technical landscape of invention]

Conventional silicon transistors, especially in the manufacture of high-output transistors, generally use a method to prevent current concentration by installing a resistor in series with the emitter as a measure against ASO (safe operating area). Here is an example.

High output transistor, frequency is about 100M1lz,
For devices with an output of 100 W, the current flowing through the emitter is very large, so a separate emitter method is adopted, so that each single emitter in a group of emitters in the same device works equally, and current concentration does not occur. Each resistor is formed in series with each single emitter. Here, the resistor is made by diffusing phosphorus at an arbitrary concentration into polycrystalline silicon, which is performed separately from other heat treatments. On the other hand, since hundreds of emitters are formed in a square base area, the patterning technique requires a fine etching technique of several microns.

The manufacturing method of the above-mentioned example is shown in FIGS. 1 to 7 and will be explained below. First, a silicon oxide film (4) is formed on the exposed surface of the N layer (2) of a silicon substrate (3) having an N layer (2) on the N+ layer (1), and this is used to form a base region by photolithography. The silicon oxide film in the planned area is removed to selectively form a P-type base region (5) (FIG. 1).

Next, a P+ layer (6) is placed on the surface of the silicon oxide III (
Similarly, hundreds of emitter regions (71, (force/
... (one of which is shown) is formed by providing an opening in the oxide film on the surface (FIG. 2).

Next, a P-doped polysilicon layer (8') is formed by depositing polysilicon on the entire surface and diffusing phosphorus (FIG. 3).

The P-doped top 9 layer (8 layers) is photo-etched to form a resistive layer (8) in a predetermined shape (FIG. 4).

Next, the P+ layer (6) and the emitter region +7), (
7) Silicon oxide + vague (5
a) with respective openings (6b), (7a), (7a)-
(Figure 5).

Next, an aluminum electrode film is deposited and photo-etched to form a connection layer (9) between the emitter region and the resistor layer.
t9)..., emitter electrode (9E
).

(9E)..., base electrode from which the P+ layer is derived (9B)
, and a predetermined wiring pattern (not shown) including the above is selectively left (FIGS. 6 and 7).

[Problems with background technology]

The above conventional method has the following problems.

First, in the formation of the first layer, there is a step of opening a silicon oxide film in the area where the first layer is to be formed by photolithography, a step of depositing an impurity source and heat treatment for introducing P+ impurities, an oxidation step for protecting the P+ layer, etc. Requires many steps.

Next, for the formation of the silicon oxide film used for preserving the P+ layer, an oxidation process called hydrogen combustion hydrochloric acid oxidation, which emphasizes extremely cleanliness, is used to obtain surface stability.

In addition, the oxidation process promotes a decrease in the impurity concentration in the surface layer of the base layer, thereby hindering the stabilization of Table 1ni.

Furthermore, when a fine pattern as described above is required, defects are likely to occur in the electrode lead-out portion, resulting in many technical problems.

[Purpose of the invention]

In view of the above conventional problems, this invention simplifies the process and
An improved method for manufacturing a semiconductor device is provided to improve polarization and reliability of the device.

[Summary of the invention]

A method for manufacturing a semiconductor device according to the present invention includes depositing a polysilicon layer on the exposed portion of an active region of a different conductivity type formed with an exposed portion on one main surface of a silicon substrate,
A doped oxide layer doped with a conductive material having the same conductivity type as that of each region is deposited on the exposed portion of each region, and then heated and simultaneously diffused to form an electrode lead-out film and insulate it at the same time. The method is characterized in that a doped polysilicon resistor is formed on the film, the electrode leading film and one end of the resistive film are connected through a metal layer, and an electrode is provided on the other end of the resistive film.

Embodiments of the Invention Next, one embodiment of the present invention will be explained in detail with reference to FIGS. 8 to 12. Note that this example is NPN)
The manufacturing of a transistor will be exemplified, and since the steps shown in FIG. 1 are the same as conventional ones, the following steps will be described in detail.

Next, holes are formed in the silicon oxide layer (5a) on the surface by photolithography to selectively form several hundred emitter regions (force, (7)...
・(The figure shows one of them). Next, a base electrode lead-out hole (6a) and an emitter electrode lead-out hole (7a) are formed in the silicon oxide film (5a) by photolithography in the same manner as described above (FIG. 8).

Next, a polycrystalline silicon layer (lυ) is deposited on the entire surface, and BSG IIaD is further deposited by CVD to form a P+ layer.
This layer is left on the base electrode lead-out hole (6a) by photolithography (FIG. 9).

Next, a PSG film u3+ for forming a single N layer is laminated by CVD over the entire surface, and then heat treatment is performed to form a P-type high concentration diffusion layer and an N-type low-strength diffusion layer in the polycrystalline silicon layer Uυ. (Figure 10).

Next, a hole (6a) for leading out the base electrode is formed by photolithography.
A P-type hole concentration diffused polycrystalline silicon layer (lla) is formed on the top, an N-type low-degree diffusion polycrystalline silicon layer (llb) for leading out the emitter region is formed on the emitter electrode lead-out opening (7a), and further on the silicon oxide IN. A resistive layer (llcl) of the N-type low concentration polycrystalline silicon layer is left in each of the substrates.
), a shallow P+ diffusion layer (5c) is formed in the 11th
figure).

Next, an aluminum electrode film is deposited on the entire surface and photo-etched to form connection layers (12c), (12c), etc. between the emitter region (force, (7)... and the resistance layer (llc)).・
, an emitter electrode (IIE) on the resistance layer (11c), (
IIE) - Selectively leave the base arctic layer (12B) and a predetermined wiring pattern (not shown 1113) including the above (FIGS. 12 and 13).

〔Effect of the invention〕

According to this invention, when forming a resistance layer formed of an N-type low concentration diffused polycrystalline silicon film on a polycrystalline silicon film, at the same time, a P-type high-density diffused polycrystalline silicon film is formed to facilitate the derivation of a base electrode. This has the following advantages.

(Al　The manufacturing process can be significantly shortened.

(bl) The oxidation process and impurity introduction heating process are reduced, and the reliability of the device is significantly improved.

(c, 1) The number of photo-etching steps for the oxide film is reduced and the means for leading out the electrodes becomes easier, reducing the occurrence of defects.

[Brief explanation of drawings]

1 to 6 are cross-sectional views showing a conventional semiconductor device manufacturing method in the order of steps; FIG. 7 is a top view of FIG. 6;
8 to 12 are cross-sectional views showing the method of manufacturing a semiconductor device of the present invention in the order of steps with reference to FIG. 1, and FIG. 13 is a top view of FIG. 12. 5 Base region 5a Silicon oxide film 5c P+ diffusion layer 7.7... Emitter region 11 Polycrystalline silicon layer 11a P-type highly diffused polycrystalline silicon layer 11b N-type low concentration diffused polycrystalline silicon 7 layer 11c Shallow P+ diffusion Layer 12 BSG film (boron silicate glass) 12B Base electrode 12E Emitter electrode 13 PSGII! ! (Phosphorsilicate Glass) Agent Patent Attorney Kazuo Inoue Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure γ1=jsa'7B Figure 8 Figure 10

Claims (1)

[Claims] A polysilicon layer is deposited on the exposed portions of active regions of four different conductivity types formed with exposed portions on one main surface of a silicon substrate, and a polysilicon layer is deposited on the exposed portions of each of the conductivity types of each region. A doped oxide layer doped with a conductive material exhibiting the same conductivity type is deposited, then heated and simultaneously diffused to form a five-pole conductive film and at the same time a doped polysilicon resistive film is formed on the insulating layer. 1. A method for manufacturing a semiconductor device, comprising: forming an electrode-leading film and one end of a resistive film by a metal layer, and providing an electrode at the other end of the resistive film.