JPS60169974U - Noise removal circuit - Google Patents

Noise removal circuit

Info

Publication number
JPS60169974U
JPS60169974U JP5583384U JP5583384U JPS60169974U JP S60169974 U JPS60169974 U JP S60169974U JP 5583384 U JP5583384 U JP 5583384U JP 5583384 U JP5583384 U JP 5583384U JP S60169974 U JPS60169974 U JP S60169974U
Authority
JP
Japan
Prior art keywords
circuit
noise removal
hold
noise
removal circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5583384U
Other languages
Japanese (ja)
Inventor
菅井　義郎
木村　裕行
Original Assignee
パイオニア株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by パイオニア株式会社 filed Critical パイオニア株式会社
Priority to JP5583384U priority Critical patent/JPS60169974U/en
Publication of JPS60169974U publication Critical patent/JPS60169974U/en
Pending legal-status Critical Current

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  • Television Receiver Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

図は本考案の一実施例のブロック図である。 ４・・・マトリックス回路、５１　および５゜・・・サ
ンプルアンドホールド回路、７・・・タイミング設定回
路、訃・・モード切換回路。The figure is a block diagram of an embodiment of the present invention. 4... Matrix circuit, 51 and 5°... Sample and hold circuit, 7... Timing setting circuit, 5... Mode switching circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] マトリックス回路の出力をサンプルアンドホールドする
サンプルアンドホールド回路と、ノイズ検出信号または
ノイズに同期したホールドパルスをサンプルアンドホー
ルド回路に供給するタイミング設定回路とを備えたテレ
ビジョン音声多重信号復調回路の雑音除去回路において
、テレビジョン音声多重信号復調のモードにしたがって
前記ホールドパルス幅を変化させるようにしたことを特
徴とする雑音除去回路。Noise removal for a television audio multiplex signal demodulation circuit that includes a sample and hold circuit that samples and holds the output of a matrix circuit, and a timing setting circuit that supplies a noise detection signal or a hold pulse synchronized with the noise to the sample and hold circuit. 1. A noise removal circuit characterized in that the hold pulse width is changed according to a mode of demodulating a television audio multiplexed signal.
JP5583384U 1984-04-18 1984-04-18 Noise removal circuit Pending JPS60169974U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5583384U JPS60169974U (en) 1984-04-18 1984-04-18 Noise removal circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5583384U JPS60169974U (en) 1984-04-18 1984-04-18 Noise removal circuit

Publications (1)

Publication Number Publication Date
JPS60169974U true JPS60169974U (en) 1985-11-11

Family

ID=30578875

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5583384U Pending JPS60169974U (en) 1984-04-18 1984-04-18 Noise removal circuit

Country Status (1)

Country Link
JP (1) JPS60169974U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57162582A (en) * 1981-03-30 1982-10-06 Mitsubishi Electric Corp Noise eliminating circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57162582A (en) * 1981-03-30 1982-10-06 Mitsubishi Electric Corp Noise eliminating circuit

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