JPS6016988Y2 - Key interface circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a key interface circuit suitable for use in, for example, a push-button dial telephone and is particularly suitable for integration.

Recently, telephones have been put into practical use that employ pushbutton dials instead of conventional rotary dials.

In this type of telephone, an oscillation circuit is controlled in response to the operation of each button to generate a dial signal.

Conventionally, this oscillation circuit has two circuits, one for high group frequency and one for low group frequency.
Two tank circuits were provided, and the constants of each tank circuit were switched in accordance with the operation of each button to obtain the required output.

In other words, each button was provided with contact pieces for high group frequencies and low group frequencies, as well as a common contact piece, and the required output was mechanically created by these complex switch groups.

As a result, the configuration of the switch group becomes extremely complicated, and since the switch is directly interposed in the tank circuit for switching, there are problems such as the inability to resonate if contact resistance increases due to aging, corrosion, etc.

Therefore, there was a desire for a switch with a simple mechanical configuration that could maintain safe operation over a long period of time.

As a device that meets these demands, there is a device shown in FIG. 1 that has been used in desktop electronic computers and the like.

In other words, this is the switch S that works with each button.
ll, S12. S21. It consists of a switch section 1 in which S22 are arranged in a matrix, and a key interface circuit 2 that outputs an output according to the operation of this switch section 1.

This key interface circuit 2 includes P-channel MOS type transistors TRI and TR2 whose drains are connected to connecting terminals H1 and H2 corresponding to the horizontal rows of the switch section 1, respectively, and whose sources are grounded, and connecting terminals L corresponding to the vertical columns.
l, inverter II connected to L2, 12, said transistor TR1.

Drain of TR2 and inverter 11. Resistors R1 and R for connecting the input part of I2 to the negative potential VDD, respectively.
2, R3, and R4.

In this configuration, so-called multiphase clock pulses HH1 and HH2 having different times as shown in FIG. 2 are constantly applied to the gates of transistors TRI and TR2.

Each time the clock pulses HHi and HH2 are input, the drains of the transistors TRI and TR2 go to a high level. For example, when the switch S12 is turned on, a high level is taken out to the connection terminal L2, which is inverted by the inverter 2, and a low level is sent to the output terminal LL2. The output of is retrieved.

By the way, an output is generated at the output terminal LL2 when either the switch S12 or the switch S22 is turned on, but the identification is performed by means such as ANDing the clock pulses HH1 and HI3 and the output.

Thus, this key interface circuit requires multiphase clock pulses.

However, since telephones do not inherently have a source of such multiphase clock pulses, key interface circuits such as those described above are unsuitable for use in telephones.

Also, automatic dialing devices are sometimes added to telephones, but in this case too, the key interface circuit as described above may be inconvenient.

In other words, even when inputting information corresponding to on/off of a switch from an external logic circuit as an automatic dialing device, it must correspond to the above-mentioned clock pulse.

Unless this external logic circuit has a clock pulse synchronized with the above clock pulse, an additional circuit 3 as shown in FIG. 3 is required.

This is the AND gate Gl, G2. G3. G4 and an OR gate G5, H1', )12', L1', and L2' are external inputs corresponding to the horizontal and vertical columns of the switch section 1.

This additional circuit 3 has a clock pulse HHi. It takes out the external logic circuit output corresponding to HI3. For example, to obtain the output corresponding to turning on the switch Sll, inputs H1' and L1' of the external logic circuit should be grounded, and inputs H2' and L2 should be connected to the ground potential.
' should be set to a negative potential.

As described above, conventional key interface circuits have various disadvantages when applied to telephones.

The present invention was developed in view of the above-mentioned circumstances, and its purpose is to reduce the influence of contact resistance of the switch means and to enable operation without using clock pulses, especially for pushbutton type telephones. It is an object of the present invention to provide a key interface circuit suitable for application to and suitable for integration.

An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 4, Hl and R2 are connection terminals connected to horizontal rows of a switch section formed by connecting a plurality of switches in a matrix, Ll and Ll are connection terminals connected in a column, and connection terminals H1, H2 has multi-connector type PN
The bases of the P transistors 11, 12 are connected to the connecting terminal Ll.

The bases of NPN transistors 13 and 14 are connected to Ll, respectively.

Each emitter of said transistor 11.12 is connected to a first current supply.

In this embodiment, this first current supply section is a power supply terminal (2) to which a predetermined positive voltage is applied.

. and this power terminal ■.

. A resistor 15 is connected to the resistor 15 at one end, and each emitter is connected to the other end of the resistor 15.

In addition, each emitter of transistors 13 and 14 is connected to the ground terminal E.
connected to.

Resistors 16 and 17 are interposed between the emitters and bases of these transistors 13 and 14, respectively, and their collectors are connected to output terminals Lll and L12.

A multi-collector type NPN transistor 18.19 is provided between one collector of the transistor 11.12 and the output terminals H1l, H12.
The output format in 12 is Lll.

It acts as an inverter to match that of L12.

Further, the other collectors of these transistors 18 and 19 are commonly connected to a common output terminal HIO.

Resistor 20.21 is a resistor connected between the base and emitter of transistor 18.19, and this emitter is connected to ground terminal E.

Note that the other collectors of the transistors 11 and 12 are connected to the base, and this produces the following effects.

That is, by connecting the other collector of transistor 11.12 to the base, transistor 11.1
The base current of No. 2 is added with the collector current of the other collector to become a large current, which is supplied from the connection terminals H1 and H2 to the bases of the transistors 13 and 14 via switches (not shown) and connection terminals Ll and L2, respectively. That will happen.

Therefore, these transistors 13 and 14 operate with a large base current, and even if induced noise is generated, the noise current is transferred to the transistor 1.
Even if it mixes into the base current of 3.14, the S/N ratio of the base current can be kept high, so malfunction of transistors 13.14 due to the noise can be prevented, and operational reliability can be improved.

In such a configuration, when all the switches in the switch section are off, the transistors 11, 12, 13, 14,
18.19 is also in the off state.

For example, if the switch between connection terminals H1 and Ll is turned on, the power supply terminal ■.

. The emitter of the transistor 11 is connected through the resistor 15.
Current flows through the base, the connection terminal H1, the switch, the connection terminal L1, the base/emitter of the transistor 13, and the connection terminal E.

As a result, transistors 11 and 13 are turned on, and the collector of transistor 11 becomes high level, and the collector of transistor 13 becomes low level.

Further, when the transistor 11 is turned on, the transistor 18 is turned on, and each collector of the transistor 18 is also at a low level.

That is, when the switch between the connection terminals H1 and L1 is turned on, the output terminals H1O and Hl1°Lll all become low level.

By setting the output terminal Lll to a low level, it is possible to determine which column the information belongs to, and by setting the output terminal H1l to a low level, it is possible to identify which row in the column corresponding to the output terminal Lll the information belongs to.

Note that the output obtained from the common output terminal HIO is 1. It can be used for powering on and controlling an oscillation circuit for generating dial signals of a telephone.

As mentioned above, in the key interface circuit according to the present invention, when any switch among a plurality of switches connected in a matrix is turned on, the information of the column and row corresponding to the switch that is turned on is output. .

Therefore, which switch in the same row was turned on is
It is identified using multiphase clock pulses as in conventional circuits.

As described above, since the present circuit does not require multiphase clock pulses, it is convenient for application to telephones that do not have a multiphase clock pulse source.

Further, since it is not a pulse operation but a DC operation, even when an automatic dialing device or the like using an external logic circuit is added, an additional circuit for dealing with clock pulses is not required, which is convenient.

In other words, to obtain information corresponding to the switch operation, the connection terminals H1 and H2 are set to low level, and the connection terminals Ll and L2 are set to low level.
should be set to a high level.

Furthermore, in this circuit, the emitter and base of transistors 11 and 12 and the base and emitter of transistors 13 and 14 are connected in series by a switch, so each transistor operates with current, and as a result, the contact resistance of the switch decreases over time. Even if the base voltage of the transistor changes due to changes or the like, it can operate extremely stably compared to voltage-operated circuits.

For example, a transistor can normally operate if a base current of several + μA flows, and therefore it can operate even if the contact resistance of the switch increases to about 10 OKΩ, and its operation stability is extremely high.

In other words, transistors can operate even at low voltages, and as a result, extremely stable operation can be ensured even when applied to telephones that require consideration of loss due to line length, etc. suitable.

In addition, in the case of telephones, an oscillation control circuit is provided after the key interface circuit, and this oscillation control circuit is equipped with an IIL (Integrated IIL) that operates stably at low voltage.
Injection Logic) circuits are often used.

Although this IIL circuit is current-operated, the output sections of the key interface circuit according to the present invention are all current-sucking types, so it is convenient to use them by directly connecting them to such subsequent circuits.

Furthermore, the circuit of the present invention has a simple configuration, can be easily formed into a bipolar integrated circuit, and is convenient for integration into equipment.

As described above, according to the present invention, even if the contact resistance of the switch means increases, it will not be significantly affected by this, and without using clock pulses, it is convenient when applied to telephones etc. Logic circuit information can also be input in parallel, and it can be used for various button application devices.
Furthermore, it is possible to provide a key interface circuit that can be directly coupled to the IIL circuit configuration stage circuit.

[Brief explanation of drawings]

Fig. 1 is a wiring diagram showing a conventional key interface circuit, Fig. 2 is a time chart of clock pulses used in the key interface circuit of Fig. 1, and Fig. 3 is a wiring diagram showing an additional circuit of the conventional key interface circuit. FIG. 4 is a wiring diagram showing a key interface circuit according to an embodiment of the present invention. 11.12...PNP transistor, 13,1
4...NPN transistor, 15, 16, 17
・・・・・・Resistance L 18. 19---NPN transistor, 20.21... Resistor.

Claims (1)

[Scope of utility model registration request] In the key interface circuit for obtaining the opening/closing information of the switching means, the emitter is connected to the first N-flow supply, and a multi-collector is configured, the first collector of which is connected to the first output, and the second collector is connected to the first N-flow supply. is connected to its base, and its emitter is connected to a second
an NPN transistor connected to the current supply section of the transistor and whose collector is connected to the second output section, and the switching means is inserted between the bases of each of these transistors, and when the switching means is turned on, the 1 to the emitter-base switching means of the PNP transistor and the base-switching means of the NPN transistor.
A key interface circuit characterized in that a current is passed through a path between an emitter and a second current supply section to turn on each transistor, and its collector output is output from each of the first and second output sections.