JPS60168251A - Address conversion control system - Google Patents

Abstract

PURPOSE:To reduce the increase of overhead with respect to time to use efficiently a pipeline by using an actual address as a converted address if logical addresses coincide with each other in a system having two address conversion mechanisms. CONSTITUTION:Actual addresses obtained from address conversion buffers 2 and 11 are transferred to registers 6 and 15. If data in a desired address is not held in a data buffer, contents of registers 6 and 15 are set to an address register 19 to access a main storage device, and the converting operation is executed by an address converting circuit. Thereafter, if conversion is necessary in another main storage access request, the logical address in a register 34 which is stored in the main storage device and the logical address to be converted in a register 35 are compared with each other before the converting operation; and if coincidence is detected, write to an address conversion buffer is performed in accordance with the preceding result remaining in the register 34.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to an address translation control method for increasing the speed of a processing device of an information processing system, particularly a processing device of a virtual storage type and a pipeline control type. .

(b) Background of the Technology A pipeline system is used as one of the control systems to improve the processing speed of central processing units, vector processing units, and the like. In this method, the execution sequence of each instruction is divided into multiple stages, and each stage is configured to be able to operate independently, thereby making it possible to execute multiple instructions simultaneously in parallel.

The execution sequence of each instruction is divided into 12 cycles, as shown in FIG. 1, for example. The function of each cycle is as per the outline method.

I: Instruction fetch address calculator: Instruction address translation buffer access B: Instruction buffer data access D-Instruction decoding R: Register read A; Operand address calculation T ni Operand address translation buffer access B: Operand buffer data Access E1: Operation execution cycle 1 E2: Operation execution cycle 2 V: Chesok cycle W: 11. In order to make the most advanced use of the inclusive cycle pipeline system, different instructions need to be assigned and executed in parallel so that there is no slack in the circuits that execute each of the cycles. In this way, if the data necessary for instruction execution can be continuously supplied to the pipeline, 1
Execution of one instruction is completed in each cycle, and the highest processing speed can be obtained.

In the above sequence, 1-T-B and A-T
Each of the three cycles of -B is a sequence of instruction fetch and data access, respectively. This sequence is
The process is completed in three cycles as shown only if the address of the desired instruction or data is in the address translation buffer and the desired instruction or data is in the buffer storage; otherwise, the transfer to main memory is completed. Due to address conversion processing or data access that requires access,
It takes more processing cycles. Therefore, the storage capacity, control system, etc. of the address translation buffer and buffer storage device are designed with consideration given to increasing the probability of holding necessary data as much as possible.

Furthermore, each instruction execution sequence includes two access cycles (1-T-B and A-T-B), so if you try to execute all cycles in parallel as described above, both Access conflicts must be resolved. To this end, a method is adopted in which a data access mechanism consisting of an address translation buffer and a buffer storage device is provided separately for instruction fetch and operand access so that both mechanisms can operate in parallel.

(C1 Prior Art and Problems) Although such a system in which two sets of data access mechanisms are provided can speed up processing through advanced use of pipelines, the following problems may occur.

(i) The same contents may be registered in both address translation buffers, reducing the usage rate of the address translation buffers.

(ii) Address translation processing when the target address does not exist in the address translation buffer may be duplicated for the same address area for instruction addresses and operand addresses, increasing time overhead.

This phenomenon is particularly likely to occur in a small-scale subroutine module where the addresses of the instruction part and operand area of the program are close to each other.

In this case, (i) above can be considered unavoidable in order to increase speed, but (ii) is a process that requires access to the main memory as described above, and increasing the number of accesses will increase speed. Improvement was desired as this could be a factor that inhibits.

(d) Object of the Invention Accordingly, it is an object of the present invention to provide an address translation control method that improves the above-mentioned drawbacks, causes little increase in time overhead, and makes highly efficient use of pipelines.

(e1 Structure of the Invention) This object of the present invention is to convert a logical address into a real address in an address translation control method that separately has an address translation buffer for operand access and an address translation buffer for instruction fetch in a virtual memory processing device. and means for outputting the real address as a translated address, means for storing a pair of a logical address last translated by the means and a corresponding real address, and when the operand address or instruction fetch address does not exist in the address translation buffer. prior to the execution of the address translation in the storage means, the method further comprises means for setting the real address stored in the storage means as the translated address when the logical address stored in the storage means matches the logical address to be translated; This is achieved by an address translation control method characterized by the following.

(Example of f1 invention Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 is a block diagram showing an example of the configuration of the processing device. The processing device consists of three functional units, an I-41E unit 42 and an S unit 43, and a buffer storage device 44. ■Uniso 1-41 decodes instructions and controls the entire pipeline. The E unit 42 performs calculations in instruction execution. S unit 43 controls address conversion between logical addresses and real addresses and access to buffer storage 44 and main storage 45. Buffer storage device 4
4 is provided for the purpose of speeding up effective access to the data by holding a copy of a portion of the data on the main storage device 45.

In general, an access request to the main memory is issued from the unit 7) 41 to the S unit 43, processed by the S unit 43, and if the desired data is on the buffer storage device 44, it is transferred to the main storage device 45. The data is read from the buffer storage device 44 without being directly accessed and supplied to the (1) unit 41 or the E unit 42. When there is no target ψ data in the buffer storage device 44 and in the case of a write request, S
In the unit 43, the main storage device 45 is accessed. The S unit 43 converts logical addresses into real addresses for access to buffer storage and main memory. In order to speed up this conversion, an address conversion buffer, which will be described later, is provided. If the address translation buffer does not contain the target address, it is necessary to index the address translation table stored in the main memory and perform address translation.

The present invention mainly relates to a control system for an S unit, particularly an address conversion circuit thereof.

FIG. 3 shows two of the address translation mechanisms to which the present invention is applied.
This part consists of a set of address translation buffers and data buffers. In the figure, 2 and 11 are address translation buffers for operand access and instruction processing, respectively, and 4 and 13 are data buffer mechanisms for operands and instructions, respectively.

The operand access address and instruction fetch address are set in OER register l and IER register lO, respectively.

In the system of this embodiment, the address translation buffer translates a 19-bit logical page address into a real page frame address, and each of address translation buffers 2 and 11 corresponds to the 1st to 11th pinto parts of the logical page address. It is composed of two sets of buffers each having 256 items each pairing with a real page address.

Two items are simultaneously read from the address translation buffer 2 or 11 using the 12th to 19th bits of the logical page address, and the comparison circuit 3a compares the 1st to 11th pins of 0ER1 or IERIO with the logical address field of the read item.
and 3b, or 12a and 12b. As a result of the comparison, there are cases where one comparison circuit detects a match, and cases where both comparisons result in a mismatch.

When a matching output is obtained from the comparison circuit, the real page address corresponding to that logical address is sent to the data buffer mechanism 4 or 1.
Pass it to 3. Each of the data buffer mechanisms 4 and 13 is a known circuit consisting of, for example, a 64-byte data block 64 (16I) of high-speed memory and its control circuit, and is not directly related to the present invention, so no further explanation will be given. Not performed.

The real address obtained from the address translation buffer is ORR
Or, if the data has been transferred to the IRR register 6.15 and the data at the desired address is not saved in the data buffer, the contents of 0RR6 or IRR15 are sent to the main memory address register MAR19, and the data is transferred to the main memory 45. Access is made.

Comparison circuit, both 3a and 3b, or 12a and 12b
When a mismatch is detected between the two, the address conversion circuit 30
Accordingly, a conversion operation using the address conversion table stored in the main storage device 45 is executed. This conversion operation will be explained with reference to FIG.

The address conversion table has two layers in total and consists of a segment table and a page table, and the contents of each item in the segment table indicate the start address of each page table. The start address of the segment table is I unit 4
It is stored in the control register within 1.

In the case of the above mismatch, the logical address written to IERl or 0ERIO is written to the TLR register 31. Also, the segment table start address (STO) is transferred from the control register of the I unit 41 to the TRP register 32.
cents. Next, STO on TRP32 and TLR
An adder 33 adds the page address of the logical address on 31 to obtain an access address to an item in the segment table. This address is IERl or 0ER on line 38.
The data is sent to IO, main memory access is executed using the method described above, and the page table start address, which is data read from the main memory, is sent to the TRP 32.

Next, the page table start address on TRP32 and T
By adding the logical page address on LR31 with the adder 33 and accessing the main memory using this address as before, the desired real page address is read from the page table, sent to TRP32, and 1' R
The contents of P32 are transferred to TWR register 34.

The logical address, the contents of TLR 31, is then transferred via line 38 to OERl or IERIO, with part of that address selecting one entry in the address translation buffer and adding another part of the logical address to that entry on line 39. The contents of the TWR 34 transferred through the TWR are written. This registers the new address pair in the address translation buffer and makes it available for subsequent accesses.

The above is an outline of the conversion operation similar to that in the conventional system, but in the embodiment of the present invention, when the real page address is determined by the above operation and the TWR 34 is sent,
At the same time, the logical address on the TLR 31 is set in the TLRH register 35. Therefore, the contents last registered in the address translation buffer are also stored in the address translation circuit 30 as a pair of TWR 34 and T L RH 35.

After that, when another main memory access request requires conversion by the address conversion circuit 30, "I" is used as before.
When a logical address is set in LR31, the contents of TLRH35 and TLR31 are compared by comparison circuit 36 prior to the conversion operation. If a match is detected here, without performing the conversion operation using the address conversion table in the main memory, it is immediately assumed that the address conversion has been completed based on the previous result left in the TWR 34, and the address conversion is transferred to the address conversion buffer. Write.

If the contents of the T L RH 35 do not match the logical address to be translated, address translation processing is performed as in the conventional example. However, if the conversion is successful, TLRH3 is
5 and TWR34 are updated and saved.

As a result of the above, if an address translation request for accessing the same page occurs consecutively for instruction fetch and operand access, the subsequent address translation request will be completed without accessing the address translation table in main memory. I can do this 9-.

Note that the contents stored in the TWR 34 and TLRH 35 must naturally match the contents of the corresponding item in the address translation buffer. Therefore, when all or part of the contents of the address translation buffer are forcibly made non-AJ,
At the same time, it must be configured to invalidate or erase the contents of TWR 34 and TL Rl 35. Such forcible invalidation of the address translation buffer is performed by executing specific instructions such as when changing the address translation table, so the contents of TWR34 and TLRH35 are also included in those instructions at the same time. It is desirable to merge the function of erasing.

(G1 Effect of the Invention As is clear from the above explanation, if the present invention is applied to an address translation mechanism, two sets of instructions, one for instruction fetch and one for operand access, can be used to speed up a pipelined central processing unit. In a system with an address translation mechanism, there is almost no possibility that both address translation mechanisms perform redundant address translation processing using the address translation table in the main memory for the same address area. You can change the effect.

[Brief explanation of drawings]

Figure 1 is a diagram showing the instruction execution sequence of the processing device, Figure 2 is a diagram showing the instruction execution sequence of the processing device.
3 is a block diagram of the processing device, FIG. 3 is a block diagram of an address translation buffer and its surroundings, and FIG. 4 is a block diagram of the address translation circuit. In the figure, 2 and 11 are address translation buffers, 4 and 13 are data buffer circuits, 30 is an address translation circuit, 41 is a ■ unit, 42 is an E unit, 43 is an s unit, 44 is a buffer storage device, and 45 is a main memory It is a device. Koto 1 Mouthhole 2 Illustration rate 3 Mouth

Claims (1)

[Claims] (11 Hypothesis 1. In an address translation control method in which an address translation buffer for operand access and an address translation buffer for instruction fetch are separately provided in an α-based processing device, a logical address is translated into a real address. , means for outputting the real address as a translated address, means for storing a pair of a logical address last translated by the means and a corresponding real address, and an operand address or an instruction fetch address existing in an address translation buffer.
Before executing the address conversion in the case where the address conversion is not performed, the real address stored in the storage means is converted until the logical address recorded in the storage means matches the logical address to be converted. An address conversion control method characterized by having means for converting an address into an address. (2) When at least a part of the contents of at least one of the address translation buffer for operand access and the address translation buffer for instruction fetch is forcibly invalidated, a means for simultaneously erasing the contents of the storage means is provided. An address conversion control method according to claim (1).