JPS60167342A - Aging device - Google Patents

Aging device

Info

Publication number
JPS60167342A
JPS60167342A JP2162684A JP2162684A JPS60167342A JP S60167342 A JPS60167342 A JP S60167342A JP 2162684 A JP2162684 A JP 2162684A JP 2162684 A JP2162684 A JP 2162684A JP S60167342 A JPS60167342 A JP S60167342A
Authority
JP
Japan
Prior art keywords
aging
defective
ics
tester
wirings
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2162684A
Other languages
Japanese (ja)
Inventor
Takashi Akazawa
赤沢 隆
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP2162684A priority Critical patent/JPS60167342A/en
Publication of JPS60167342A publication Critical patent/JPS60167342A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PURPOSE:To effectively utilize the aging time of ICs by a method wherein a proper screening inspection of the ICs is contrived so as to be able to perform during the aging time, and at the same time, some ICs determined to be defective are made to be destroyed during the aging time. CONSTITUTION:Aging substrates 2, on each of which plural ICs 3 have been set, are housed in an aging stove, and at the same time, a tester 16 and a breaking unit 17 are respectively connected to the prescribed connector parts of the aging substrates 2. A test signal is inputted in each IC3 from the tester 16 through connector parts 15 for each signal and wirings 14 for each signal and the desired screening inspection of the ICs 3 is performed. During such the test, the tester 16 performs a decision on non-defective and defective of each IC3 on the basis of the response signal, which is sent from each IC3, specifies the positions of defective ICs 3 decided to be a defective on the aging substrates 2 and gives a breaking instruction to the breaking unit 17. The breaking unit 17 changes over a first and a second change-over switches 8 and 9 corresponding to an appointed position on the basis of the breaking instruction, turns off a third and a fourth wirings 6 and 7, impresses a reverse bias on the defective IC3 through the two wirings 6 and 7 and makes the defective IC3 destroy electrically.

Description

【発明の詳細な説明】 〔技術分野〕 本発明は、エージング技術、たとえば、県債回路や大規
模集積回路を形成されてなる半導体装置(以下、ICと
いう。)についてのエージング技術に使用17て有効か
技術に閣する。
[Detailed Description of the Invention] [Technical Field] The present invention is applicable to aging technology, for example, aging technology for semiconductor devices (hereinafter referred to as ICs) formed with prefectural bond circuits and large-scale integrated circuits. It depends on the technology whether it is effective or not.

〔背景技術〕[Background technology]

ICの初期不良等の発見にエージングを行う場合、まず
、エージング前に予備的な選別検査を行って既に不良に
なったICを排除し、エージング後、本来の選別検査を
行ってエージングで不良になったICを排除する方法が
考えられる。
When aging is used to detect initial defects in ICs, first, a preliminary screening test is performed before aging to eliminate ICs that have already become defective, and then after aging, the original screening test is performed to identify those ICs that have become defective due to aging. A method can be considered to eliminate the IC that has become.

しかし、このようなエージング方法においては、エージ
ング中は選別検査が行われないため、時間が有効利用で
きないきいう問題点があることが、本発明者によって明
らかにされた。
However, the inventor of the present invention has found that in such an aging method, there is a problem in that time cannot be used effectively because no screening inspection is performed during aging.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、エージング時間を有効利用することが
できるエージング技術を提供することにある。
An object of the present invention is to provide an aging technique that can effectively utilize aging time.

本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述および添付図面から明らかになるであろう
The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

〔発明の概要〕[Summary of the invention]

本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、次の通りである。
A brief overview of typical inventions disclosed in this application is as follows.

すなわち、エージング中に適当な選別検査を行なえるよ
うに構成するとともに、不良が発見されたものについて
は破壊させることができるように構成することにより、
エージング時間を有効利用できるようにしたものである
In other words, by configuring the product to be able to perform appropriate screening inspections during aging, and to destroy products found to be defective,
This allows for effective use of aging time.

〔実施例〕〔Example〕

第1図は本発明の一実施例であるエージング装置を示す
概略正面図、第2図はエージング基板を示す拡大部分平
面図である。
FIG. 1 is a schematic front view showing an aging device as an embodiment of the present invention, and FIG. 2 is an enlarged partial plan view showing an aging substrate.

本実施例において、このエージング装置はエージング炉
1を備えており、この炉1は炉内の温度雰囲気を加熱装
置や空気循環装置等(図示せず)により所望の高温に維
持されるようになっている。
In this embodiment, this aging device is equipped with an aging furnace 1, and the temperature atmosphere inside the furnace 1 is maintained at a desired high temperature by a heating device, an air circulation device, etc. (not shown). ing.

エージング炉1はその内部に複数のエージング基板2を
出入自在に収納できるように構成されており、エージン
グ基板2は被エージング物としてのIC3を機械的およ
び電気的にかつ着脱自在に複数接続し得るように構成さ
れている。
The aging furnace 1 is configured so that a plurality of aging substrates 2 can be freely stored therein, and the aging substrates 2 can be mechanically and electrically connected to a plurality of ICs 3 as objects to be aged in a detachable manner. It is configured as follows.

第2図に示されているように、エージング基板2には、
工C3のV。C端子3aに接続される第1配線4と、I
C3のグランド(G)端子3bに接続される第2配線5
と、第1配線4とは別に工C3のV。0端子3aに接続
される第3配線6と、第2配線とは別にIC3のG端子
3bに接続される第4配II7とがそれぞれ形成されて
おり、容重C3に対応して、第1配線4と第3配線6と
の間、第2配)15と第4配線6との間には、第1.第
2切換スイッチ8,9が通常時は第1配線4側および第
2配線5側を閉じるようにそれぞれ介設されている。第
1−第4配線4〜7はエージング基板2の一端面に配設
された第1〜第4コネクタ部10゜11.12.13に
それぞれ接続されている。
As shown in FIG. 2, the aging substrate 2 includes:
Engineering C3 V. The first wiring 4 connected to the C terminal 3a and the I
The second wiring 5 connected to the ground (G) terminal 3b of C3
And, apart from the first wiring 4, the V of the engineering C3. A third wiring 6 connected to the G terminal 3a of the IC 3 and a fourth wiring II7 connected to the G terminal 3b of the IC 3 are formed separately from the second wiring. 4 and the third wiring 6, and between the second wiring 15 and the fourth wiring 6. Second changeover switches 8 and 9 are interposed so as to close the first wiring 4 side and the second wiring 5 side under normal conditions. The first to fourth wirings 4 to 7 are connected to first to fourth connector portions 10, 11, 12, and 13 disposed on one end surface of the aging board 2, respectively.

また、エージング基板2には多数のテスト信号入出力用
配線14が容重C3の信号端子3Cに対応してそれぞれ
配線されており、これら配線14はエージング基板2の
両側面に配設された信号用コネクタ部15にそれぞれ接
続されている。
In addition, a large number of test signal input/output wirings 14 are wired on the aging board 2 in correspondence with the signal terminals 3C of the capacity C3, and these wirings 14 are connected to the signal terminals 3C arranged on both sides of the aging board 2. Each is connected to the connector section 15.

エージング炉1にはテスタ16と、このテスタ16に連
携された破壊装置17とが接続されており、テスタ16
は各エージング基板2における第1、第2コネクタ部1
0,11および信号用コネクタ部15に、破壊装置17
は各エージング基板2における第3.第4コネクタ部1
2.13に、適当な接続手段を介してそれぞれ接続され
るようになっている。
A tester 16 and a destruction device 17 linked to the tester 16 are connected to the aging furnace 1.
are the first and second connector parts 1 in each aging board 2
0, 11 and the signal connector part 15, the destructive device 17
is the third. in each aging board 2. 4th connector part 1
2.13, respectively, through suitable connection means.

次に作用を説明する。Next, the action will be explained.

複数のIC3をセットしたエージング基板2をエージン
グ炉1内に収納させるとともに、エージング基板2の所
定のコネクタ部にテスタ16および破壊装置17をそれ
ぞれ接続させる。
The aging board 2 on which a plurality of ICs 3 are set is housed in the aging furnace 1, and a tester 16 and a destruction device 17 are respectively connected to predetermined connector portions of the aging board 2.

エージング炉1が加熱され所定の温度雰囲気が作られた
状態において、テスタ16からエージング基板2を介し
て各IC3に電源電圧が印加される。すなわち、テスタ
16−第1コネクタ部10−第1配線4−第1切換スイ
ッチ8−、ICのV。0端子3a−ICのG端子す一第
2切換スイッチ9−第2配線5−第2コネクタ部11−
テスタ16と通電される。
In a state where the aging furnace 1 is heated and a predetermined temperature atmosphere is created, a power supply voltage is applied from the tester 16 to each IC 3 via the aging board 2. That is, tester 16 - first connector part 10 - first wiring 4 - first changeover switch 8 - and V of IC. 0 terminal 3a - IC G terminal 1 - 2nd changeover switch 9 - 2nd wiring 5 - 2nd connector section 11 -
The tester 16 is energized.

この印加状態において、テスタ16から各IC3にテス
ト信号が各信号用コネクタ部15、各信号用配線14を
通じてそれぞれ入出力され、所望の選別検査が実施され
る。このとき、エージング時間は通常1〜2時間と長期
にわたるため、比較的長時間を要するテスト事項を選定
することが望ましい。また、高温状態において発生し易
い不良に関するテスト事項を選定することも有効である
In this application state, test signals are inputted and outputted from the tester 16 to each IC 3 through each signal connector section 15 and each signal wiring 14, and a desired selection test is performed. At this time, since the aging time is usually long, 1 to 2 hours, it is desirable to select test items that require a relatively long time. It is also effective to select test items related to defects that are likely to occur in high-temperature conditions.

但し、高温状態においてテストを行うと、必然的に不良
が発生する事項についてはテストを行うべきでない。ま
た、エージング中にテストを行うためには、テスタ、エ
ージング基板等の構造が複雑になり過ぎる事項等につい
ては、コストパフォーマンスの観点からも取捨選択すべ
きである。
However, tests should not be conducted on items that will inevitably cause defects if tested at high temperatures. In addition, in order to conduct tests during aging, items such as testers and aging boards that would require too complicated structures should be selected from the viewpoint of cost performance.

このようなテスト中、テスタ16は容重C3からの応答
信号により良不良の判定を行い、不良と判定したIC3
のエージング基板2上における位置を特定し、破壊装置
17に破壊指令を与える。
During such a test, the tester 16 determines whether the IC3 is good or bad based on the response signal from the IC3 that is determined to be defective.
The position on the aging board 2 is specified, and a destruction command is given to the destruction device 17.

破壊装置17はこの指令に基き、指定された位11!に
対応する第1.第2切換スイッチ8.9を切り換えて第
3.第4配線6,7側を閉じ、両配線6゜7を通じて不
良のIC3に逆バイアスをかけこのiC3を電気的に破
壊させる。
Based on this command, the destruction device 17 is placed at the specified position 11! The first corresponding to Switch the second selector switch 8.9 to the third switch. The fourth wirings 6 and 7 are closed, and a reverse bias is applied to the defective IC 3 through both wirings 6° 7 to electrically destroy the IC 3.

〔効 果〕〔effect〕

ill エージング中に適描な選別検査を行うことによ
り、長期間を要するエージング時間を有効利用すること
ができる。
By performing appropriate screening tests during aging, the long aging time can be effectively utilized.

(2) 長期間にわたるテスト事項をも取り入れること
により、選別検査の信頼性を高めることができる。
(2) The reliability of screening inspections can be increased by incorporating test items over a long period of time.

(31発見された不良品を直ちに破壊してしまうことに
より、後で再検査してしまう危険がなくなり、作業性が
向上できる。
(31) Immediately destroying discovered defective products eliminates the risk of re-inspecting them later and improves work efficiency.

以上本発明者によってなされた発明を実施例に基づき具
体的に説明したが、本発明は前記実施例に限定されるも
のではなく、その要旨を逸脱しない範囲で種々変更可能
であることはいうまでもない0 たとえば、破壊手段としては、逆バイアスをかける構成
に限らず、順方向に高電圧をかける構成であってもよい
Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the Examples and can be modified in various ways without departing from the gist thereof. For example, the destruction means is not limited to a configuration that applies a reverse bias, but may also be a configuration that applies a high voltage in the forward direction.

〔利用分野〕[Application field]

以上の説明では主として本発明者によってなされた発明
をその背景となった利用分野であるICのエージング技
術に適用した場合について説明したが、それに限定され
るものではなく、たとえば、他め電子部品、電子機器、
電気部品、電気機器についてのエージング技術にも適用
できる。
In the above explanation, the invention made by the present inventor was mainly applied to the aging technology of IC, which is the background field of application, but it is not limited to this, and for example, other electronic components, Electronics,
It can also be applied to aging technology for electrical parts and equipment.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示す概略正面図、第2図は
エージング基板の拡大部分平面図である。 1・・・エージング炉、2・・・エージング基板、3・
・IC(被エージング物)、4,5,6,7.14・・
・配線、8,9・・・切換スイッチ、10,11゜12
.13.15・・・コネクタ部、16・・テスタ、17
・・破壊装置。
FIG. 1 is a schematic front view showing an embodiment of the present invention, and FIG. 2 is an enlarged partial plan view of an aging board. 1... Aging furnace, 2... Aging substrate, 3...
・IC (aging object), 4, 5, 6, 7.14...
・Wiring, 8, 9... Selector switch, 10, 11゜12
.. 13.15... Connector part, 16... Tester, 17
...Destruction device.

Claims (1)

【特許請求の範囲】 1、所定の温度雰囲気を作るエージング炉と、この炉内
に収容され、被エージング物を保持して給電するエージ
ング基板と、この基板に保持された被エージング物に適
当なテスト信号を入力し、かつ被エージング物からの応
答信号をモニタして良不良を判定するテスタと、不良と
判定された被エージング物を破壊する破壊手段とを備え
ているエージング装置。 2 破壊手段が、被エージング物に逆バイアスをかける
通電回路により構成されていることを特徴とする特許請
求の範囲第1項記載のエージング装置。
[Claims] 1. An aging furnace that creates an atmosphere at a predetermined temperature, an aging substrate that is housed in this furnace and holds an object to be aged and supplies power, and an aging furnace that is suitable for the object to be aged held on this substrate. An aging device that includes a tester that inputs a test signal and monitors response signals from an aging object to determine whether it is good or bad, and a destruction means that destroys an aging object that is determined to be defective. 2. The aging device according to claim 1, wherein the destruction means is constituted by an energizing circuit that applies a reverse bias to the object to be aged.
JP2162684A 1984-02-10 1984-02-10 Aging device Pending JPS60167342A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2162684A JPS60167342A (en) 1984-02-10 1984-02-10 Aging device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2162684A JPS60167342A (en) 1984-02-10 1984-02-10 Aging device

Publications (1)

Publication Number Publication Date
JPS60167342A true JPS60167342A (en) 1985-08-30

Family

ID=12060271

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2162684A Pending JPS60167342A (en) 1984-02-10 1984-02-10 Aging device

Country Status (1)

Country Link
JP (1) JPS60167342A (en)

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