JPS60165823A - Waveform equalizing device - Google Patents

Abstract

PURPOSE:To improve the converging and stability performance by reproducing a comparatively stable data clock signal from an equalizing output signal and using the data clock signal to provide a more accurate reference signal where the shift of zero cross point of the equalizing output signal is suppressed. CONSTITUTION:The adaptive algorithm by means of the least square error method is realized except the generation of a reference signal in the basic operation of the titled device. Delay lines 10 and 11-1-11-5, in this case, correct the time delay for the generation of the reference signal by retarding equally a V0 and each tap output. When the equalization is incomplete, a zero cross detection signal is a signal inverted at a phase different from that of an original signal by means of the shift of zero cross point of the equalized output. When the shift amount of the zero cross point is not extremely larger in this case either, a discriminating output signal is operated invertingly at the phase of the trailing edge of the regenerated data clock just after the signal inversion of the zero cross detection signal takes place in order than the regenerated data clock signal represents a correct phase. Moreover, the regenerated data clock signal is a signal suppressing the phase fluctuation of the data clock of the equalized output signal by a phase synchronism circuit 8 and gives a comparatively stable phase.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a waveform equalization device in a magnetic tape device for recording and reproducing pulse code modulated signals.

Conventional Structures and Problems In recent years, devices have come into use that pulse-encode acoustic signals and record and reproduce them on magnetic tape.

In this case, high-density trace recording is performed, and waveform equalization is essential for effective use of the recording/reproduction frequency band, and development of waveform equalization devices that automatically perform this is progressing.

A conventional waveform equalization device will be explained below with reference to FIGS. 1 and 2. (1-1) to (1-5) are 5-tap delay lines in which the delay amount between each tap is Td, (2-1) to
(2-5) is the tap output and weighting coefficients W1, W2,
. . . A multiplier that outputs the product with W5, and an adder 3 that outputs the sum of the multiplier outputs. These constitute a 5-tap I-Lance Bar V Luno Filter. 4 is a detector that detects the zero cross of the output vO of the recruitment device 3 and outputs a reference signal V ref which is 1 when vO≧O and -1 when vO is 0; 5 is the difference between vO and V ref; This is a subtractor that outputs a certain error signal Ve. (6-1) ~ (6-
5) is a multiplier that outputs the product of each tap output and Ve;
(7-1) to ('1-5) are multipliers (6-1) to (6-
The cumulative value of the output of step 5) is input and the weighting coefficients W1 to W5 are input.
This is an integrator that outputs .

The waveform equalizer configured as described above uses the least square error method (
least vean 5quare error l
1ethOd), and realizes an adaptive algorithm in which W1 to W5 change so as to always minimize the root mean square of Ve.

When a reproduction signal from a magnetic tape device is input to this waveform equalizer, as shown in Fig. 2, the output signal vO has a steep rise or fall and its amplitude is constant.
As a result, a waveform close to the signal recorded on the magnetic tape device is obtained, and the recording/reproducing characteristics of the magnetic tape device are corrected. When W1 to W5 are optimized as described above, the zero-crossing point shift of the reproduced signal caused by the limitation of the signal band due to the recording and reproduction characteristics is reduced. Furthermore, the second
In the figure, a is the original signal, b is the input signal Vi, c is the output signal VO, d is the reference signal V ref, α and β are the shift amounts of the Z[] cross point, and α>β.

However, in the above conventional configuration, the reference signal is determined using the zero-crossing point of the equalized output signal, and the average square error between this reference signal and the equalized output is reduced, so the reference signal is pulse code modulated. The resulting signal was not an ideal signal, and had poor convergence and stability.

OBJECTS OF THE INVENTION The present invention solves the above-mentioned conventional drawbacks, and an object of the present invention is to provide a waveform equalization device with high convergence and stability.

Structure of the Invention In order to achieve the above object, the waveform equalization device of the present invention includes a transversal filter section with variable tap weighting coefficients, and a phase synchronization circuit that extracts a data clock from the output signal of the transversal filter section. , a reference signal generation section including a detection circuit that detects data from the output of the transversal filter section and outputs it as a reference signal in synchronization with the data clock obtained by the phase synchronization circuit, and the transversal filter section a subtraction circuit that outputs an error signal between the output of the transversal filter section and the reference signal, a multiplication circuit that multiplies the error signal and each tap output of the transversal filter section, and a multiplication circuit that temporally integrates the multiplication results of the multiplication circuit. This configuration includes an arithmetic unit including an integrator that outputs tap coefficients of the transversal filter unit.

DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 3 is a circuit block diagram of a waveform equalizer according to an embodiment of the present invention, and has the same structure as the constituent elements shown in FIG. 1 *I!
The elements are given the same symbols. In Figure 3, (1
-1) to (1-5) are 5-tap sinusoids where the delay amount between each tap is τ, and (2-1) to (2-5) are the products of the tap output and the weighting coefficients W1 to W5. 3 is an adder that outputs the sum of the outputs of multipliers (2-1) to (2-5>), and these constitute a 5-tap transverse null filter.4 is a detector that detects the zero crossing point of the transparsil filter output ■0 and outputs the detection signal v1, 8 is a phase synchronized circuit that reproduces the data clock signal from the output of the detector 4, and 9 is obtained by the phase synchronized circuit 8. A determiner that determines the sign of Vl in synchronization with the reproduced data clock signal and outputs a reference signal Vref.

A delay line with a delay amount τ0 equal to the time delay amount from 5
is a subtracter that outputs an error signal Ve as the difference between the output of the delay line 10 and V ref. (11-1) ~ (11-
5) is a delay line with a delay amount τ0 that corrects the time delay τ0 from ■0 of Ve, and (6-1) to (6-5) are delay lines (11
-1) ~ (11-5) f) Multiplier that outputs the product of output 1 = VQ, (7-1) ~ (7-5) are multipliers (6-
The cumulative values of the outputs of 1) to (6-5) are used as weighting coefficients W1 to W5.
This is an integrator that outputs as .

The basic operation of the waveform equalizing apparatus in this embodiment configured as described above is to realize an adaptive algorithm using the least square error method, which is the same as in the conventional example except for the generation of the reference signal. However, the delay line 10 and (ti-i) to (11
-5) is a delay line for correcting the time delay for generating the reference signal by similarly delaying Vo and each tap output.

The operation of generating a reference signal will be explained below.

Figure 4 is a signal waveform diagram of each part of the circuit shown in Figure 3, where a is the original signal, b is the input signal Vi, C is the output signal Vo, d is the zero cross point detection signal, e is the reproduced data clock signal, and f
The reference signal vrθf19 is the D point shift amount compared to the detection signals 1, α, and βt, and α>β>>1γ1.

When equalization is incomplete, the zero-crossing detection signal becomes a signal that is inverted with a phase different from that of the original signal due to the zero-crossing point shift of the equalized output. However, even in this case, if the shift amount of the zero-crossing point is not extremely large, the reproduced data clock signal will display the correct phase, so the judgment output will be made at the falling phase of the reproduced data clock immediately after the signal inversion of the pyrocross detection signal occurs. Avoid inverting the signal. Further, the reproduced data clock signal is obtained by suppressing the phase fluctuation of the data clock of the equalized output signal by the interphase +11J circuit 8, and provides a relatively stable phase.

By operating as described above, a reference signal that is inverted with almost the same phase as the original signal can be obtained even if there is a slight zero point shift in the input signal. According to the series of operations described above, even if there is a slight zero-crossing point shift in the equalized output signal, it is possible to provide an accurate reference signal, that is, a reference signal close to the original signal.

As described above, according to this embodiment, IC automatic equalization can be realized using a more accurate reference (ffi number) than in the conventional example.
Convergence and stability are significantly improved.

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, a relatively stable data clock signal is recovered from an equalized output signal, and the data clock signal is used to suppress the zero-cross point shift of the equalized output signal. Since a reference signal is provided, convergence and stability can be greatly improved.

[Brief explanation of drawings]

FIG. 1 is a circuit block diagram of a conventional waveform equalizer, FIG. 2 is a signal waveform diagram of each part of the circuit shown in FIG. 1, and FIG. 3 is a circuit block diagram of a waveform equalizer according to an embodiment of the present invention. , FIG. 4 is a signal waveform diagram of each part of the circuit shown in FIG. 3. (1-1) ~ (1-5), (10), (11-1) ~ (
11-5)...Delay line, (2-1) to (2-5), (
6-1) ~ (6-5)...Medical device, 3...-Kashiki device,
4...Detector, 5...Subtractor, (7-1) to (7-
5)...Integrator, 8...Phase synchronized circuit, 9...Determiner agent Yoshihiro Morimoto

Claims (1)

[Claims] 1. A transversal filter section whose tap coefficient is variable, a phase synchronized circuit that extracts a data clock from the output signal of this transversal filter section, and a phase synchronized circuit that extracts a data clock from the output signal of this transversal filter section; It has a reference signal generation section that includes a detection circuit that detects data from the output of the transversal filter section and outputs it as a reference signal, and also outputs an error signal between the output of the transversal filter section and the reference signal. a multiplication circuit that multiplies the error signal by each tap output of the transversal filter section;
1. A waveform equalization device comprising an arithmetic unit comprising an integrator that temporally integrates the multiplication result of the cursor and outputs the result as a tap coefficient of the transversal filter unit.