JPS6016478A - Semiconductor element - Google Patents

Abstract

PURPOSE:To form the titled element of characteristics with less dispersion and of high performance with a good yield by a method wherein the impurity region part and the electrode part of said element are constructed on the substrate of the element at the position of recesses. CONSTITUTION:The semi-insulation GaAs crystal substrate 11 is coated with a photo resist 12, which is then formed into a required pattern by exposure and development. With the resist 12 of this pattern as a mask, the recesses 13 of a fixed depth are formed in the substrate 11 by etching. Next, an impurity is ion-implanted from above the recess 13 at the position for constructing a conductive layer part, with the resist 12 as a mask; thereafter the resist 12 of the required pattern is removed. Then, the conductive layer part 14 of a Hall element is constructed by heat treatment. The electrode 15 are provided in the recesses at the position for electrode arrangement formed by etching, and a wafer is cut into every required chip, resulting in the assembly of the Hall element 16.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, in which a recess is formed on the surface of a semiconductor device substrate corresponding to an impurity region or an electrode portion of the semiconductor device, and a semiconductor device is formed on the semiconductor device substrate at the location of the recess. To provide a semiconductor device which has uniform characteristics and high performance by configuring an impurity region portion or an electrode portion, and which is easy to manufacture and has an improved yield. With the goal.

For example, a Hall element is constructed as shown in FIG. 1 or 2, in which a conductive layer is formed by ion-implanting impurities into a semi-insulating GaAs substrate, and an electrode portion is provided on the surface.

In other words, the mesa-etch Hall element shown in FIG.
Without forming an implantation pattern, ions of an impurity such as SI are implanted into the GaAs substrate 1, and then heat treatment is performed to activate the impurity.
A conductive layer is uniformly formed on the surface of the As substrate 10, and then a Hall element pattern is formed by a four phosphorography process, and portions other than those to be made into a conductive layer are removed by etching to form a conductive layer with a predetermined Hall element pattern. 2, and then an electrode 3 was provided at a predetermined position.

However, the Hall element constructed in this manner requires a step of forming a mesa shape by chemical or dry etching, which has disadvantages such as a complicated process and high cost.

Therefore, a planar type Hall element has been proposed as shown in FIG. A window for ion implantation is formed in the upper layer, ions are implanted to form a conductive layer with a predetermined pattern, and then a photoresist or 5i0
It has been proposed that a conductive layer 6 having a predetermined pattern is formed by removing an insulating film layer such as No. 2 and performing heat treatment, and then providing an electrode 7 at a predetermined position.

However, although the Hall element constructed in this way has a simpler manufacturing process than the aforementioned Hall element,
Products with a small unbalanced voltage VO are manufactured less frequently, and
This method has disadvantages in that it is easy to produce a device with a large input resistance Ri, the characteristics of the Hall element vary widely, and the manufacturing yield of high-performance Hall elements is low.

The present invention eliminates the above-mentioned drawbacks, and examples thereof will be described below.

3a to 3c are explanatory diagrams of the manufacturing process of a semiconductor device according to the present invention, and FIG. 4 is an explanatory diagram of the completed semiconductor device.

That is, as shown in FIG. 3a, for example, semi-insulating G
A photoresist 12 is applied to the aAs crystal substrate 11, and the photoresist 12 is exposed and developed to form a predetermined pattern.

Next, as shown in the same figure, using this predetermined pattern of photoresist 12 as a mask, recesses 13 of a predetermined depth and a predetermined pattern are formed in the GaAS crystal substrate 11 by etching. The depth a of the recess 13 at the position corresponding to the portion constituting the conductive layer portion to be described later is approximately the same as the depth b of the conductive layer portion formed by ion implantation to be described later. It is desirable to make it slightly thicker.

Then, using the photoresist 12 as a mask, impurity ions are implanted from above the concave portion 13 at the position constituting the conductive layer portion (ion implantation conditions: dose amount 8×1012 ions107
1% injection voltage (190 KeV) l, then the predetermined pattern of photoresist 12 is removed, and heat treatment (annealing conditions: 800° C., 7 minutes) is performed to form the conductive layer of the thread element as shown in FIG. 3C. 14.

Further, the electrode 15 is provided at the position where the electrode part of the Hall element is to be provided, that is, in the concave part of the electrode arrangement position formed by the etching process in the step of FIG. A Hall element 16 as shown in the figure is constructed and assembled as shown in FIG. In the same figure, 17 is mold resin, 18 is A lead wire, 19
is a lead frame.

When the Hall element is constructed as described above, that is, when the surface of the GaAs substrate at the electrode placement position is etched to form a recess, the GaAs substrate surface at the electrode placement position is cleaned when the electrode is provided. Therefore, there is little variation in the input resistance R1 of the Hall element.Since the surface of the GaAs substrate where the electrodes are arranged is depressed, this depression serves as a landmark and helps in pattern alignment when configuring the electrodes. It is easy, the electrodes can be formed accurately, and the work can be carried out efficiently.

Furthermore, if the surface of the GaAs substrate at the location where the conductive main part is formed is etched to form a recess, when ions of impurities are implanted, the surface of the GaAs substrate at the ion-implanted portion is clean, so that impurities other than the intended impurities are kept clean. Impurities such as constituent materials of photoresist are not implanted, and the input resistance Ri of the Hall element has little variation, and it is easy to obtain a small unbalanced voltage Vo. If the peripheral edge of the recess is configured accurately, and in particular, the depth of this recess is approximately the same as or slightly deeper than the depth of the conductive layer to be configured, the conductive layer will be configured accurately and the unbalanced voltage V .

is small and has little variation.

For example, a case where a Hall element is made by etching a concave part on the same GaAs wafer as in this example, and a case where a Hall element is made by etching and forming a concave part as in this example, and a case where the same GaAs wafer is etched and a concave part is not formed as a comparative example and the same as the conventional 1;+<( In addition, the unbalanced voltage was 0.2, whereas the average value of the pole element of this example was 0.92 and the standard deviation was 0.74. , the Hall element of the comparative example has an average value of 1.48 and a standard deviation of 1.01.
In addition, as shown in Fig. 6, which shows the distribution diagram of ■0 (the solid line is the present example, the dotted line is the comparative example), many of the unbalanced voltages Vo are small, and high-performance Hall elements can be manufactured with a high yield. It shows that

As described above, in the semiconductor element according to the present invention, four parts are formed on the surface of the semiconductor element substrate corresponding to the impurity region part or the electrode part of the semiconductor element, and the impurity region part or the electrode part of the semiconductor element is formed on the semiconductor element substrate at the position of the recess. Since the electrode portion is configured, it has the advantage that semiconductor devices with uniform characteristics and high performance can be obtained at a high yield.

[Brief explanation of the drawing]

Figures 1 and 2 are explanatory diagrams of a conventional Hall element, Figures 3a-c are illustrations of the manufacturing process of a Hall element according to an embodiment of the present invention, and Figure 4 is an explanatory diagram of a Hall element according to an embodiment of the present invention. An explanatory diagram of
Fig. 5 is an explanatory diagram of the state in which the Hall element of Fig. 4 is incorporated, and Fig. 6 shows the Hall element 11...GaAs crystal substrate (semiconductor element substrate), 13... recess, 14...・
Conductive layer portion (impurity region portion), 15... electrode. Patent applicant: Katsumi Utaka, agent of Victor Japan Co., Ltd. (t1 times ↑5, Figure 16)

Claims (1)

[Claims] A semiconductor device characterized in that a recess is formed on the surface of a semiconductor element substrate corresponding to an impurity region or an electrode of the semiconductor element, and the impurity region or electrode of the semiconductor element is formed on the semiconductor element substrate at the position of the recess. .