JPS6016452A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPS6016452A
JPS6016452A JP58124455A JP12445583A JPS6016452A JP S6016452 A JPS6016452 A JP S6016452A JP 58124455 A JP58124455 A JP 58124455A JP 12445583 A JP12445583 A JP 12445583A JP S6016452 A JPS6016452 A JP S6016452A
Authority
JP
Japan
Prior art keywords
chip
film
heat
cap
semiconductor integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58124455A
Other languages
Japanese (ja)
Inventor
Takashi Tokura
戸倉　隆
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP58124455A priority Critical patent/JPS6016452A/en
Publication of JPS6016452A publication Critical patent/JPS6016452A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/71—Means for bonding not being attached to, or not being formed on, the surface to be connected
    • H01L24/72—Detachable connecting means consisting of mechanical auxiliary parts connecting the device, e.g. pressure contacts using springs or clips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE:To enable to obtain the route for thermal conduction also from the surface of a chip by a method wherein the upper part of an insulating surface protection film is provided with a thermally conductive metallic film having no electrical relation with the circuit in the chip. CONSTITUTION:A chip substrate 1 is mounted on a case base material 5, chip terminals 2' being bonded to the case 5, and then a metallic spring 8 is inserted between the metallic film 4 on the chip surface and the cap 6 at the time of sealing with the cap 6. Such a structure enables the effect of heat dissipation of the heat from the chip 1 to multiply by the realization of the route from the film 4 through the spring 8 to the cap 6.

Description

【発明の詳細な説明】 （１）発明の属する技術分野 本発明は半導体集積回路の構造に関し、特に発熱量の大
きい集積回路の放熱効果を上げるための構造に関する。DETAILED DESCRIPTION OF THE INVENTION (1) Technical field to which the invention pertains The present invention relates to the structure of a semiconductor integrated circuit, and particularly to a structure for increasing the heat dissipation effect of an integrated circuit that generates a large amount of heat.

（２）従来技術の説明 従来半導体集積回路（以下チップと呼ぶ）内で発生する
熱？放熱する方法としては、チップのサブストレート側
則ち裏面をセラミックに密着させてこの面からの熱伝導
により熱を逃がす構造又は、チップの表面の端子部を同
様な母材に接続し裏面に放熱用のフィンを付けてこのフ
ィンへの熱伝導により熱を逃がす構造がとられていたた
めいずれもチップの裏面からしか熱伝導の経路がなく、
チップの発熱量の制限もしくは発熱量に応じて放熱フィ
ンの表１釦面積會大きくする必要があるという欠点があ
った。(2) Description of conventional technology Heat generated in conventional semiconductor integrated circuits (hereinafter referred to as chips)? Heat dissipation methods include a structure in which the substrate side of the chip, that is, the back surface, is brought into close contact with ceramic and heat is dissipated through heat conduction from this surface, or a structure in which the terminals on the front surface of the chip are connected to a similar base material and heat is dissipated from the back surface. In both cases, the only route for heat conduction was from the back of the chip, as the structure was such that heat was dissipated by attaching fins to the fins and conducting heat to the fins.
There is a drawback that the area of the heat dissipation fin needs to be increased due to limitations on the amount of heat generated by the chip or in accordance with the amount of heat generated.

（３）発明の目的 不発明の目的はチップの裏面からだけではなくチップの
表面からも熱伝導の経路全提供することにより、上記欠
点を解決し放熱効率の良いチップ実装構造を提供するこ
とにある。(3) Purpose of the Invention The purpose of the invention is to solve the above drawbacks and provide a chip mounting structure with high heat dissipation efficiency by providing all paths for heat conduction not only from the back side of the chip but also from the front surface of the chip. be.

（４）　発明の構成 不発明は１通常のチップにおいて端子部を除く表面領域
が絶縁性の保護膜で復われていることに着目し、この膜
の上部にチップ内の回路と電気的に無関係の熱伝導性の
金属膜を設けた構造にすることによル従来裏面だけの熱
伝導路にゆだねていた構造に１表面からも熱伝導路葡提
供するものである。(4) Structure of the invention The non-invention is 1. Focusing on the fact that the surface area of a normal chip except for the terminal area is covered with an insulating protective film, there is a layer on the top of this film that is electrically unrelated to the circuit inside the chip. By creating a structure in which a thermally conductive metal film is provided, a heat conduction path is provided from one surface as well, whereas the structure conventionally relied on a heat conduction path only from the back surface.

（５）実施例 次に図面全参照して本発明の実施例について説明する。(5) Examples Next, embodiments of the present invention will be described with reference to all the drawings.

第１図は不発明のチップ構造図である。第２図は本発明
の断面図であシ、絶縁性保護膜の上に金属膜全村けた構
造を示している。FIG. 1 is a diagram showing the structure of a non-inventive chip. FIG. 2 is a cross-sectional view of the present invention, showing a structure in which a metal film is entirely formed on an insulating protective film.

従来のチップは第３図の断面図に示すように最上膜は絶
縁性保護膜で覆われておシ１本発明はこの膜の上に熱伝
導性の金属膜を付した構造を特徴としている。As shown in the cross-sectional view of Figure 3, the conventional chip has a top layer covered with an insulating protective film.1 The present invention is characterized by a structure in which a thermally conductive metal film is attached on top of this film. .

第４図は不発明の効果を明確にする実装構造例を示して
いる。従来技術でチップをセラミック等のケースにマウ
ントし、チップ端子部とケースをボンディングし、キャ
ップで封入する際。FIG. 4 shows an example of a mounting structure that makes the effect of the invention clear. When using conventional technology to mount a chip in a ceramic case, bond the chip terminals to the case, and encapsulate it with a cap.

本発明によるチップ表面の金属膜とキャップの間に金属
性のバネを挿入した構造である。不構造にすることによ
り従来チップの熱はチップ裏面と接するセラミックを通
して伝導するのみであったものが、不発明による表面膜
からノ（ネを通してキャップに達する経路が実現できる
ことにより、放熱の効果が従来に比べて倍増するのは明
像である。This structure has a metal spring inserted between the metal film on the chip surface and the cap according to the present invention. Conventionally, by making the chip unstructured, the heat of the chip was only conducted through the ceramic in contact with the back side of the chip, but by creating a path from the surface film to the cap through the hole, the heat dissipation effect has been improved. It is the bright image that doubles compared to the .

（６）発明の効果 不発明は以上説明したように、チップの表面にも熱伝導
路を提供することにより従来の裏面からの熱伝導に比べ
てチップ内の発熱を外に逃がす効果が加速され、チップ
内温度上昇を押える効果もしくは従来発熱のため制限さ
れていたチップ内ｕ路密度全上げうる効果がある。(6) Effects of the invention As explained above, by providing a heat conduction path on the surface of the chip, the effect of dissipating heat inside the chip to the outside is accelerated compared to the conventional heat conduction from the back surface. This has the effect of suppressing the temperature rise within the chip or increasing the total density of U-paths within the chip, which was previously limited due to heat generation.

さらには１表面が金属膜で覆われているため。Furthermore, one surface is covered with a metal film.

化学的処理をしない限りチップ内の回路ノくターンの解
読が出来ず秘密保護の効果並びに外部からの誘４全防止
するシールド効果もあられれる。The circuit patterns inside the chip cannot be deciphered unless chemical processing is performed, which provides a shielding effect that protects secrecy and completely prevents temptation from outside.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は不発明の構造をボす斜視図である。第２図は第
１図Ａ−Ａ’面の１所面図であり、第３図は従来のチッ
プ断面図である。第４図は不発明の実施例を示すもので
あり、該チップをケースにマウントした時の断面図ｔあ
られす。 なお図において、１・・・・・・チップ基板、２・・・
・・・表面保護膜、３・・・・・・端子部、３′・・・
・・・端子部金属膜。 ４・・・・・・表面金属膜、５・・・・・・ケース母材
、６・・・・・キャップ、７・・・・・・ボンディング
ワイヤ、８・・・・・・金属バネ型フィン、矢印は熱の
伝導経路、である。FIG. 1 is a perspective view showing the inventive structure. FIG. 2 is a view taken along line AA' in FIG. 1, and FIG. 3 is a sectional view of a conventional chip. FIG. 4 shows an embodiment of the invention, and is a cross-sectional view when the chip is mounted in a case. In the figure, 1... chip substrate, 2...
...Surface protective film, 3...Terminal section, 3'...
...Terminal metal film. 4...Surface metal film, 5...Case base material, 6...Cap, 7...Bonding wire, 8...Metal spring mold The fins and arrows are heat conduction paths.

Claims (1)

【特許請求の範囲】[Claims] 絶縁性表面保譲膜を有する半導体集積回路において、該
表面膜の上に回路と電気的接続のない熱伝導性金属膜を
配し該金属膜に熱太導性の放熱媒体ｔ−従接続たこと全
特徴とする半導体集積回路。In a semiconductor integrated circuit having an insulating surface preservation film, a thermally conductive metal film having no electrical connection with the circuit is disposed on the surface film, and a thermally conductive heat dissipating medium T-subconnection is provided to the metal film. Semiconductor integrated circuit with all its characteristics.
JP58124455A 1983-07-08 1983-07-08 Semiconductor integrated circuit Pending JPS6016452A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58124455A JPS6016452A (en) 1983-07-08 1983-07-08 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58124455A JPS6016452A (en) 1983-07-08 1983-07-08 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS6016452A true JPS6016452A (en) 1985-01-28

Family

ID=14885941

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58124455A Pending JPS6016452A (en) 1983-07-08 1983-07-08 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS6016452A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03170525A (en) * 1989-10-23 1991-07-24 Hoechst Celanese Corp Catalyst for manufacture of polyothylene terephthalate from low dialkyl ester and glycol of dicarboxylic acid
JPH06177288A (en) * 1992-12-03 1994-06-24 Nec Corp Semiconductor device
JPH07254668A (en) * 1994-01-11 1995-10-03 Samsung Electron Co Ltd Semiconductor package for high heat dissipation

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03170525A (en) * 1989-10-23 1991-07-24 Hoechst Celanese Corp Catalyst for manufacture of polyothylene terephthalate from low dialkyl ester and glycol of dicarboxylic acid
JPH06177288A (en) * 1992-12-03 1994-06-24 Nec Corp Semiconductor device
JPH07254668A (en) * 1994-01-11 1995-10-03 Samsung Electron Co Ltd Semiconductor package for high heat dissipation

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