JPS6016431A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6016431A
JPS6016431A JP58125133A JP12513383A JPS6016431A JP S6016431 A JPS6016431 A JP S6016431A JP 58125133 A JP58125133 A JP 58125133A JP 12513383 A JP12513383 A JP 12513383A JP S6016431 A JPS6016431 A JP S6016431A
Authority
JP
Japan
Prior art keywords
semiconductor element
high thermal
electrode plate
semiconductor device
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58125133A
Other languages
Japanese (ja)
Inventor
Takashi Suzumura
隆志 鈴村
Hiromichi Yoshida
博通 吉田
Yasuhiko Miyake
三宅　保彦
Sadahiko Sanki
参木　貞彦
Tatsuya Otaka
達也 大高
Akimitsu Kobayashi
小林　明光
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Cable Ltd
Original Assignee
Hitachi Cable Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Cable Ltd filed Critical Hitachi Cable Ltd
Priority to JP58125133A priority Critical patent/JPS6016431A/en
Publication of JPS6016431A publication Critical patent/JPS6016431A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0133—Ternary Alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To reduce a thermal stress and temperature rise by forming an electrode material with a composite material of high thermal conductive material holding a low thermal expansion material and bonding element and sink to the side of high thermal conductive material with solder on the occasion of forming a semiconductor device by fixing a semiconductor element and a heat sink provided in parallel thereto on the electrode material. CONSTITUTION:An electrode material is composed of three layer composite electrode plate 2 consisting of a high thermal conductive materials 6 and 8 such as Cu, Al holding a low thermal expansion material 7 consisting of Fe-Ni alloy or Fe-Ni-Co alloy and a semiconductor element 1 is welded to the side of conductive material 6 through the soldering layer 5. An insulating material 3 is bonded adjacently to such element through the soldering layer 5 and a heat sink 4 which becomes the thermal absorbing region is welded thereon by the soldering layer 5. Thereby, thermal conductivity of composite electrode plate 2 can be increased and temperature of element 1 can be lowered.

Description

【発明の詳細な説明】 半導体装置は半導体素子、電極板、ヒートシンク板、絶
縁板等で構成されている。半導体素子は一般に半田層等
を介して電極板に接合されるが、との′電極板に対して
は半導体素子の使用中等における温度上昇に対処するた
め次の２つの特性が要求される。すなわち、その１つは
熱応力による素子又は半田層の破壊を防止するためにシ
リコン等から成る素子の熱膨張率に近似した低膨張率を
有することであシ、他の１つは半導体素子の発熱を速や
かに取り去って温度上昇を小さく抑えるだめの高熱伝導
率を有することである。これら両省性を併有する材料と
して、従来モリブデンやタングステンが熱応力の緩衝材
として一部で使用されているが、これらの金属材料は高
価である上、加工性が悪いという大きな欠点を鳴してい
る。そこで、新しい試みとして低熱膨張金属と高熱伝導
金属とから成る多層複合材の電極板が提案されている。DETAILED DESCRIPTION OF THE INVENTION A semiconductor device is composed of a semiconductor element, an electrode plate, a heat sink plate, an insulating plate, and the like. A semiconductor element is generally bonded to an electrode plate through a solder layer or the like, and the following two characteristics are required of the electrode plate in order to cope with temperature rises during use of the semiconductor element. That is, one of them is to have a low coefficient of thermal expansion that approximates the coefficient of thermal expansion of an element made of silicon or the like in order to prevent the element or solder layer from breaking due to thermal stress, and the other is to have a coefficient of thermal expansion that is close to that of an element made of silicon or the like. It has a high thermal conductivity that quickly removes heat and suppresses temperature rise. Conventionally, molybdenum and tungsten have been used as materials to buffer thermal stress as materials that have both of these properties, but these metal materials have the major drawbacks of being expensive and having poor workability. There is. Therefore, as a new attempt, an electrode plate made of a multilayer composite material consisting of a low thermal expansion metal and a high thermal conductivity metal has been proposed.

ところで、従来の半導体装置の構成は第１図に示すよう
に半導体素子１、熱応力緩衝材２′、電極板２、絶縁板
３及び熱吸収板４を半田層５等を介して次々に績み重ね
て行くものである。しかしながら、上記の多層複合電極
板を使用した場合、一般に低熱ｊ杉張拐はその熱伝４率
が小さいために、この低熱膨張Ｈの層を横切る方向の熱
抵抗が大きく、第１図のような構造の半導体装置では素
子の温度を十分低く保つことができないという問題があ
った。By the way, as shown in FIG. 1, the conventional semiconductor device has a structure in which a semiconductor element 1, a thermal stress buffer material 2', an electrode plate 2, an insulating plate 3, and a heat absorbing plate 4 are successively bonded via a solder layer 5, etc. It is something that we will continue to look at. However, when using the above-mentioned multilayer composite electrode plate, the thermal resistance in the direction across the low thermal expansion layer is large due to the low thermal conductivity of cedar paper, as shown in Figure 1. In a semiconductor device having such a structure, there is a problem in that the temperature of the element cannot be kept sufficiently low.

したがって本発明の目的は、前記した問題点を解消し、
本導体素子に加わる熱応力及び素子の温度上昇を十分小
さく保つことのできる新規な半導体装置を提供すること
にある。Therefore, an object of the present invention is to solve the above-mentioned problems,
An object of the present invention is to provide a novel semiconductor device in which thermal stress applied to a conductor element and temperature rise of the element can be kept sufficiently small.

すなわち本発明の要旨とするところは、低熱膨張材と高
熱伝導材とから成る多層複合電極板の半導体素子を塔載
する面が高熱伝導材で形成され、且つこの高熱伝導材に
直接もしくは半田層等を介して間接に半導体素子及び熱
の吸収帯の両者を塔載したことにある。ここで、高熱伝
導材としては銅、アルミニウム等が用いられ、また低熱
膨張材としてはイン・々（商品名）等のＦ’ｅ−Ｎｉ合
金、コノミール（間品名）等のＦｅ−Ｎｉ−Ｃｏ合金な
どの全域材料の他、ガラス−エポキシ樹脂等の複合プラ
スチックス材料が使用される。That is, the gist of the present invention is that the surface of a multilayer composite electrode plate made of a low thermal expansion material and a high thermal conductivity material on which a semiconductor element is mounted is formed of a high thermal conductivity material, and that the high thermal conductivity material is directly or coated with a solder layer. The reason is that both the semiconductor element and the heat absorption band are indirectly mounted through the devices. Here, copper, aluminum, etc. are used as high thermal conductivity materials, and low thermal expansion materials include F'e-Ni alloys such as In-Ni (product name), Fe-Ni-Co such as Konomil (product name), etc. Composite plastic materials such as glass-epoxy resins are used as well as bulk materials such as alloys.

以下、本発明による半導体装置の実施例について陰付の
図面と共に説明する。Embodiments of the semiconductor device according to the present invention will be described below with reference to the shaded drawings.

第２〜４図は本発明の実施例による半導体装置の主要部
品の構成を示す説明図である。2 to 4 are explanatory diagrams showing the configuration of main components of a semiconductor device according to an embodiment of the present invention.

第２崗は銅６−インノ”　（Ｆｅ−３６％Ｎｉ）’７−
銅８の３順接合電極板２を使用し、この電極板２の銅層
６側に半導体素子ｌと熱の吸収帯でるるヒートシンク４
とを塔載した例である。インパフの両面に銅６，８を配
置した理由は温度変化に対してノζイメタル効果を生じ
させないだめである。なお、この例では銅とインパの厚
さの比は１：０．５：１〜１：５：１の範囲で、また電
極相２としての全体の厚さは１〜３爾？の範囲で行なっ
たが、実際には各使用条件における熱膨張率及び熱放散
率等の面からみて最適設定に応じた電極材の構成とする
ことができる。The second layer is copper 6-inno” (Fe-36%Ni)'7-
A three-order bonded electrode plate 2 of copper 8 is used, and a heat sink 4 with a semiconductor element l and a heat absorption band on the copper layer 6 side of the electrode plate 2 is used.
This is an example that includes the following. The reason for arranging the copper 6 and 8 on both sides of the in-puff is to prevent a metal effect from occurring due to temperature changes. In this example, the ratio of the thickness of copper to impurity is in the range of 1:0.5:1 to 1:5:1, and the total thickness of the electrode phase 2 is 1 to 3 mm. However, in reality, it is possible to configure the electrode material in accordance with the optimum settings in terms of thermal expansion coefficient, heat dissipation coefficient, etc. under each usage condition.

第３図は銅６−インパ７−銅８の３層重極板２の半導体
素子ｌを塔載した同じ銅層６側に熱放散を目的とした放
熱フィン９を設けたｉ＋ｌＪである。FIG. 3 shows an i+lJ in which a three-layer heavy electrode plate 2 of 6 copper, 7 impurities, and 8 copper is provided with radiation fins 9 for heat dissipation on the side of the same copper layer 6 on which the semiconductor element 1 is mounted.

第４図は熱の吸収を冷却水を用いて行なう場会、多層電
極板２の半導体素子１を塔載した高熱伝導層６側に冷却
水の循猿銅、ａイゾｌＯを絶縁材３を介して取り付けた
例である。なお、この例では半導体素子及び熱の吸収帯
を塔載した側の尚熱伝導層６をこれと反対側の間熱伝導
層８よりも厚くしているが、その理由は、？インタル効
果による反シの許容範囲内で熱の移動に大きな影響を及
ぼす前記高熱伝導層６を厚くした方が熱放散性が同上し
、従って半導体素子の温度を低下させることができるか
らである。Figure 4 shows a case in which heat absorption is performed using cooling water, and an insulating material 3 made of copper, aiso lO, and the like is used to circulate the cooling water on the side of the high heat conductive layer 6 on which the semiconductor element 1 of the multilayer electrode plate 2 is mounted. This is an example where it is attached through the In this example, the thermally conductive layer 6 on the side where the semiconductor element and the heat absorption band are mounted is made thicker than the thermally conductive layer 8 on the opposite side. What is the reason for this? This is because if the high thermal conductivity layer 6, which has a large effect on heat transfer within the allowable range due to the Intal effect, is made thicker, the heat dissipation property will be the same as above, and therefore the temperature of the semiconductor element can be lowered.

以上述べた如く、本発明によれば半導体素子に加わる熱
応力及び素子の温度上昇を十分さく保つことのできる半
導体装置を提供することができる。As described above, according to the present invention, it is possible to provide a semiconductor device that can sufficiently suppress thermal stress applied to a semiconductor element and temperature rise of the element.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来の半導体装置の主要部品め構成を示す説明
図、第２〜４図は本発明の実施例による半導体装置の主
要部品の構成を示す説明図である。 １・・・・・・半導体素子 ２・・・・・・電極材 ２′・・・・・熱応力緩衝材 ３・・・・・・絶縁材 ４・・・・・・ヒートシンク ５・・・・・半田層 ６．８・・・・・高熱伝導材 ７・・・・低熱膨張材 ９・・・・・・放熱ファン １０・・・・・・冷却水パイプ 葎　１　日 犀３日 毘　２　図 坪４図FIG. 1 is an explanatory view showing the structure of the main parts of a conventional semiconductor device, and FIGS. 2 to 4 are explanatory views showing the structure of the main parts of a semiconductor device according to an embodiment of the present invention. 1... Semiconductor element 2... Electrode material 2'... Thermal stress buffer material 3... Insulating material 4... Heat sink 5... ... Solder layer 6.8 ... High thermal conductivity material 7 ... Low thermal expansion material 9 ... Heat dissipation fan 10 ... Cooling water pipe leaf 1 Sunflower 3 days old 2 Tupyeong 4

Claims (1)

【特許請求の範囲】[Claims] 低熱膨張材と高熱伝導材とから成る多層複合半導体゛電
極板を有する半導体装置において、該電極板の半導体素
子を塔載する面が高熱伝導材で形成され、且つこの高熱
伝導相に直接もしくは半田層弄を介して間接に半導体素
子及び熱の吸収帯の雨氷発明は半導体素子を塔載した半
導体装置に関する。In a semiconductor device having a multilayer composite semiconductor electrode plate made of a low thermal expansion material and a high thermal conductivity material, the surface of the electrode plate on which the semiconductor element is mounted is formed of a high thermal conductivity material, and the high thermal conductivity phase is directly or soldered. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device mounted with a semiconductor element, which indirectly relates to a semiconductor element and a heat absorption band through a layer.
JP58125133A 1983-07-08 1983-07-08 Semiconductor device Pending JPS6016431A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58125133A JPS6016431A (en) 1983-07-08 1983-07-08 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58125133A JPS6016431A (en) 1983-07-08 1983-07-08 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6016431A true JPS6016431A (en) 1985-01-28

Family

ID=14902669

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58125133A Pending JPS6016431A (en) 1983-07-08 1983-07-08 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6016431A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1996026560A1 (en) * 1995-02-22 1996-08-29 Dilas Diodenlaser Gmbh Diode laser component with cooling element and diode laser module
WO1997030494A1 (en) * 1996-02-14 1997-08-21 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Heat sink including a surface on which an electronic component can be mounted
US6753093B2 (en) 2001-09-21 2004-06-22 Kabushiki Kaisha Toyota Jidoshokki Heat dissipating material and manufacturing method thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1996026560A1 (en) * 1995-02-22 1996-08-29 Dilas Diodenlaser Gmbh Diode laser component with cooling element and diode laser module
WO1997030494A1 (en) * 1996-02-14 1997-08-21 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Heat sink including a surface on which an electronic component can be mounted
US6753093B2 (en) 2001-09-21 2004-06-22 Kabushiki Kaisha Toyota Jidoshokki Heat dissipating material and manufacturing method thereof

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