JPS60160422A - Data processing synchronism system - Google Patents

Abstract

PURPOSE:To attain sure synchronism by switching a clock pulse application circuit with the coincidence of outputs between the 1st pulse counter counting usually a clock pulse and the 2nd pulse counter counting it normally and stopping the count at the intermission of processing. CONSTITUTION:An incoming data and an output of a shift register are synchronized by a data processing synchronism device comprising delay flip-flops 14, 15, the 1st pulse counter 16 and the 2nd pulse counter 17 or the like. The 1st pulse counter 16 counts an incoming clock pulse 8 while being reset by a timing pulse 10, the 2nd pulse counter 17 counts normally the incoming clock pulse 8 and intermits the count at the intermission of the processing. Both count values are compared by a comparator 19, and a gate 20 switching a clock pulse train 8 is controlled through the said flip-flop 14 and a gate 22 with the output of the operating discriminating circuit via gates 24, 26 together with a restart command 29 so as to attain the synchronism.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical field of the invention When processing a data string of a predetermined length under the control of an incoming clock pulse, after interrupting the processing operation, data at a predetermined position in the data string is This invention relates to a data processing synchronization method when restarting processing in synchronization.

(2) Prior Art and Problems As a conventional data processing device, there is one shown in FIG. For example, an analog signal (3) received by a receiver (2) using an antenna (1) is sent to an analog-to-digital converter (
4), it is converted into a serial digital signal (5). Next, the data is taken into the data processing device (7) as parallel data in the serial/parallel converter (6). A continuous clock pulse train (8), synchronized with the pulses for operating the analog-to-digital converter (4), is transmitted to the data processing device (7) through a transmission line (9) separate from the data train transmission line.
-1) to import. Also, a predetermined delimiter of the data string is set, for example, 1024 ([1i! data is treated as one block, and a timing pulse (I
rj is also connected to the data processing device (7
). Within the data processing device (7), the clock pulse train (8) and timing pulses (10) are utilized as follows. That is, the incoming data string is passed through the data sorting shift register (34) to the calculation pipeline (35).
), and the constant table (11) is provided in the shift register of the loop configuration in order to perform multiplication/addition processing of the output with constant data prepared in advance corresponding to the data at the predetermined position. , it is synchronously read out using a clock pulse train (8 pulses and a timing pulse 6θ), and is fed to the arithmetic unit (36) for calculation. For example, when 1024 data strings are transmitted in parallel in 32 rows, a constant table (11
), 32 lines each with 32 items, totaling 1024 pieces of data (12
-1) (1:2-2L--- is stored. Timing pulse (10) is set to be emitted simultaneously when a specific line of 32 lines of data is transferred, and the analog-to-digital converter A timing pulse α0 is obtained repeatedly at 32-row intervals from the side of (4), and the timing pulse (
Using 1φ as a trigger, by counting with a counter, the data row is shifted a predetermined number of times with respect to the shift register, timing when the first data reaches a predetermined calculation part, and the row is shifted to the output end of the constant table (13).
Be prepared so that you can get it. Next, the transmission line (9-
2) When a newer timing pulse 00) is received and the first data reaches a predetermined calculation part, the shift register is controlled to perform a shift operation, and the register data 32
Read out the data and perform arithmetic processing. When the processing of that row is finished, the clock pulse (81) is used to read out the data row of a new register every 32 pieces of data and perform arithmetic processing. Therefore, the shift register forming the constant table (11) Since the columns are shifted sequentially in a predetermined cycle, it is possible to perform accurate processing such as performing an operation corresponding to a predetermined position in the shift register.In normal processing, after setting in the above method, processing is continued repeatedly. However, when testing the operation of the device on the data processing device (7) side, reception of the clock pulse train (8) and timing pulse (10) may be interrupted. Instead of continuously using a pulse train, the test is performed by artificially incrementing the clock pulse using a pulse generator built into the data processing device (7).At that time, the digital-to-analog converter ( If the operation 4) continues, the data processing device will lose synchronization with the data string in the constant table described above.Therefore, when the test is finished, the operation described above must be restarted from the beginning, which saves time. It took a lot of effort.

(3) Object of the Invention The object of the present invention is to improve the above-mentioned drawbacks and provide a data processing synchronization method using a pulse counter so that processing can be restarted in synchronization with data at a predetermined position in a data string of a predetermined length. There is a particular thing.

(4) Structure of the Invention The structure of the present invention for achieving the above-mentioned object is to receive a data string, a clock pulse, and a timing pulse indicating a break between the data strings, and to perform a predetermined transmission under the control of the clock pulse. In a data processing synchronization method in which a data processing device that performs data processing temporarily suspends processing operations controlled by the clock pulse and resumes processing in synchronization with data at a predetermined position in a data string, the data processing device a first pulse counter that constantly counts incoming clock pulses while resetting with a timing pulse; a second pulse counter that normally counts incoming clock pulses and interrupts counting when a processing operation is interrupted; and the first and second pulses. The present invention includes a determination circuit that determines whether the outputs of the counter match and whether there is a restart command for the data processing device, and a circuit for applying clock pulses to the data processing device is opened or closed based on the output of the determination circuit.

(5) Embodiment of the Invention FIG. 3 shows, as an embodiment of the present invention, a circuit built into the data processing device (7) shown in FIG. 1 and provided in the preceding stage of the shift register shown in FIG. This circuit performs a predetermined operation to synchronize the incoming data and the shift register output. In Figure 3 (14) (15-1) (15-2)
(15-3) is a delay type flip-flop, (1
6) is a first pulse counter that counts incoming pulses while being reset by a timing pulse (10);
7) is a second pulse counter that normally counts incoming clock pulses and interrupts counting when processing operation is interrupted;
) is used to obtain an output when the decoder decodes the count value of the first pulse counter (16) and counts a predetermined value.The predetermined value is, for example, the position of the timing pulse (10) among the 32 values in Fig. The value shall be as shown. (19) is a comparator that compares the count values of the first pulse counter (16) and the second pulse counter (17) and reduces the output when they match;
) (21) (23) (26) Baand gate,
(24) indicates the Nant gate, and (22) and (25) indicate the or gate. Also, (A) are connected to each other and (P
) corresponds to output (9-1) in FIG.

(27) is a footpath pulse control terminal from a host computer (not shown), which is used during test operations to be described later. (28
) is one of the command acceptance terminals from the host computer, and the terminal becomes 1" when instructing to stop receiving the clock pulse train (8). The terminal (29) becomes "1" when instructing to resume receiving the clock pulse train (8). ” is the terminal for the pulse counter (
16) (17) and comparator (I9) gate (24) (2
6) forms an operation determination circuit. , In Fig. 3, the clock pulse train (8) is connected to the transmission line (9-
1), the flip-flop (14) is reset, "1" is output from the reset side terminal, and the terminal (
Since there is no signal at 27), the gate (20) is opened and a clock pulse is transmitted to the terminals (A) and (P). Therefore, the operation of the shift register shown in FIG. 2 is the same as the conventional one.

In addition, the clock pulse train (8) causes the flip-flop (
15-1) to (15-3) are timing pulses 0Φ
is not sent, so it is reset. The timing pulse 0ω arrives via the transmission line (9-2), centers the flip-flop (15-1), and clocks the first pulse counter (16).
and clear the count value. The number of pulses of the timing pulse train (8) that arrived thereafter is counted.

The timing pulse 00+ that resets the first pulse counter (16) is the flip-flop (15-2) (15-
3), but it is possible to obtain some delay time from the arrival of the pulse to the operational output. The second pulse counter (16) lags behind the first pulse counter (16) by that time.
17). This is because the gate (21) is open because the flip-flop (14) has not been set yet). Then, the output (A) of the gate (20) is given to the second pulse counter (17) and counted. The first pulse counter (16) and the second pulse counter (17) do not have the same count value, and even if the decoder (18) detects a predetermined value count, the input "l" is input to the terminal (2 days). ”, gates (24) and (23) will not open.

Next, when the data processing device (7) interrupts reception of the clock pulse train (8), it applies "l" to the terminal (28) in response to a command from the host computer. In this case, when the first pulse counter (16) counts up to a predetermined value, the gate (23)
is open (This means that the data from the analog-to-digital converter (4) has been received up to a value synchronized with the timing pulse. At that time, the flip-flop (14) is opened via the gate (25). Gate (2
2) gives “0” to the gate (20), so the gate (2)
0) closes and the clock pulses at outputs (A) and (P) stop. Since the second pulse counter (17) stops counting and the gate (21) closes, the timing pulse is not reset. The first pulse counter (16) continues counting. When a calculation processing clock is required for testing, etc., the host computer uses the terminal (27).
A predetermined amount of walking force is applied to the . At that time, at the same time as the operation (P), the second pulse counter (17) is also counting the number of pulses.

At the end of the test, the terminal (29) is used to instruct the host computer to resume receiving the clock pulse train (8).
give. At this time, the terminal (28) is o''.The first pulse counter (1
When 6) counts, the comparator (19) outputs a coincidence output, so the gate (24) outputs 0 due to the terminal (29) being ``1''.

0″ through gate (26) is flip-flop (14)
Reset. The gate (20) then opens again, so the clock pulse train (8) can reach (A) and (P). At this time, the data processing is synchronized since the clock (P) is continuously applied from the clock next to the clock corresponding to the timing pulse (10) shown in FIG.

(6) Effects of the Invention As described above, according to the present invention, there is provided a device which receives clock pulses and processes data when a clock pulse source is continuously operating, and which is a processing unit of a processing device which operates discontinuously. It is effective because it is possible to completely and reliably synchronize the beginning of the clock pulse train with the beginning of the processing unit of the clock pulse train using a relatively simple device. The time required for the synchronization is about the time required for counting by the first pulse counter, so it can be done in a short time.

[Brief explanation of drawings]

Figure 1 is a diagram showing a conventional data processing device, and Figure 2 is a diagram showing a conventional data processing device.
FIG. 3 is a diagram showing an embodiment of the present invention, and shows a circuit provided in the preceding stage of the shift register in FIG. 2. FIG. (ll---Antenna (2)---One receiver (3)-
...Analog signal (41--Analog-to-digital converter (51-Serial data (61--Serial to parallel converter (7)--Data processing device (8)--Clock pulse train QO)--Timing pulse (11) - m constant number table (14) (15-1) (15-2) (15-3) - delay type flip-flop (16) - first pulse counter (17) --- second pulse counter (18) ) -m-decoder (19) -comparator (20
) (21) (23) (26) Medium and gate (2
4) - Nant Gate (22) (25) - 11 OR Gate Patent applicant Fujitsu Ltd. agent Patent attorney Eisuke Suzuki

Claims (1)

[Claims] A data processing device receives transmission of a data string, a clock pulse, and a timing pulse indicating a break between the data string, and performs predetermined data processing under the control of the clock pulse.
temporarily interrupting the processing operation controlled by the clock pulse,
In a data processing synchronization method for restarting processing in synchronization with data at a predetermined position in a data string, the data processing device includes a first pulse counter that constantly counts incoming clock pulses while resetting with a timing pulse, and an incoming clock pulse. A second pulse counter that counts the energization and interrupts counting at time t11 during processing operation, and a determination circuit that determines whether the outputs of the first and second pulse counters match and the presence of a restart command for the data processing device. A data processing synchronization method comprising: a clock pulse application circuit to a data processing device is opened and closed by the output of the determination circuit.