JPS60160114A - Manufacture of semiconductor single crystal layer - Google Patents

Manufacture of semiconductor single crystal layer

Info

Publication number
JPS60160114A
JPS60160114A JP59016220A JP1622084A JPS60160114A JP S60160114 A JPS60160114 A JP S60160114A JP 59016220 A JP59016220 A JP 59016220A JP 1622084 A JP1622084 A JP 1622084A JP S60160114 A JPS60160114 A JP S60160114A
Authority
JP
Japan
Prior art keywords
layer
single crystal
semiconductor
manufacturing
crystal layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59016220A
Other languages
Japanese (ja)
Inventor
Tadashi Nishimura
正 西村
Shigeru Kusunoki
茂 楠
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP59016220A priority Critical patent/JPS60160114A/en
Publication of JPS60160114A publication Critical patent/JPS60160114A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02598—Microstructure monocrystalline
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02689—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using particle beams
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02691—Scanning of a beam

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Materials Engineering (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To single-crystallize the desired region of a semiconductor by a method wherein polysilicon is formed by irradiating linear heating radiant rays from the upper surface of a polycrystalline semiconductor layer, the position of the above irradiation is shifted in a scanning manner, a radiant ray reflecting layer is provided at a part of the semiconductor layer, and a desired heat distribution is formed. CONSTITUTION:A thermal oxide film 3, polysilicon 4, SiO2 5 and Si3N4 6 are superposed on an Si single crystal substrate 2, an Mo layer 10 is provided, and an SiO2 film 11 and an Si3N4 film 12 are covered thereon. The light L of a linearly condensed Xe arc lamp is made to irradiate on a sample 1a, polysilicon 4 is fused, and a fusion band 9 corresponding to the focussing width of the light L is formed. In the region where Mo 10 is present, the light L is reflected and Mo is fused in a narrow region only. Accordingly, the recrystallization generating due to solidification is started from said narrow region, crystal growth is also started from the lower layer of the Mo 10, and the crystal is continuously grown following the scanning of light forming a crystal grain boundary, thereby enabling to obtain a large area of single crystal Si layer.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は絶縁物層の上に半導体の単結晶層を形成する
方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for forming a semiconductor single crystal layer on an insulating layer.

〔従来技術〕[Prior art]

最近、絶縁物層、特に二酸化シリコン（Ｓ１０□）膜上
にシリコン琳結晶膜を形成する技術は５ＯＩ（８１−’
１ｉｃｏｎ　ｏｎ工ｎａｕｌａｔｉｏｎ　）技術と呼ば
れ、そして、その単結晶膜はＳＯ工と呼ばれて注目され
ている。これは従来から絶縁物上のシリコン結晶として
知られてｂる５ｏｓ（ｓ１工１ｃｅｎ　ｏｎ　５ａｐｐ
ｈｉｒｅ）が非常に高速動作をする０ＭＯ８回路に最適
といわれながら、高価であることと、本質的なシリコン
・サファイヤ界面の結晶性の悪さが改善されないのに対
して、８０ＩではＳＯＳの良さを生かしつつ、低価格お
よび界面特性の大幅な改善が可能であることに起因して
いるものである。Recently, a technology for forming a silicon phosphor crystal film on an insulator layer, especially a silicon dioxide (S10□) film, has been developed.
This single crystal film is called SO technology and is attracting attention. This is traditionally known as silicon crystal on an insulator.
Although 80I is said to be ideal for 0MO8 circuits that operate at very high speeds, it is expensive and does not improve the inherent poor crystallinity of the silicon-sapphire interface, whereas 80I takes advantage of the advantages of SOS. However, this is due to its low cost and the possibility of significantly improving interfacial properties.

しかるに、この日０工でも高品質のシリコン結晶膜をＳ
ｉＯ□膜上の広い面積に形成することは、いまだ困難で
あり、限られた面積部分を単結晶化する手法が確立して
いるのみである。特に、種結晶を用いない場合は、単結
晶化のみならず、結晶粒界の位置制御することもできて
いない状況である。However, it is possible to produce high-quality silicon crystal films even with zero labor per day.
It is still difficult to form it over a wide area on an iO□ film, and only a method of forming a single crystal in a limited area has been established. In particular, when a seed crystal is not used, not only single crystallization but also the position control of grain boundaries cannot be achieved.

その原因を説明するために、従来技術について説明する
。第１図Ａはゾーンメルティング法と呼ばれる従来の単
結晶成長方法を示す斜視図、＠１図Ｂはこれに用いられ
る基体試料の構造を示す断面図である。基体（１）は第
１図ＢＫ示すように、シリコン基板（２）上に熱酸化膜
（３）を温度９５０℃の酸化雰囲気中で５０００Ａの厚
さに形成し、これに化学的気相成長（ＯＶＤ　）方法に
よって温度６１０’Ｃで考ネ５０００Ａの厚さに多結晶
シリコン層（４）を形成した後、さらにＯＶＤ法による
厚さ２）ｔｍのシリコン酸化膜（５）およびＯＶＤ法に
よるシリコン窒化１１！（６）を設けたものである。こ
の基体（１）を第１図Ａに示すように、下部からストリ
ップヒータ（７）で１２００℃の温度に加熱保持する。In order to explain the cause, a conventional technique will be explained. FIG. 1A is a perspective view showing a conventional single crystal growth method called zone melting method, and FIG. 1B is a sectional view showing the structure of a substrate sample used in this method. As shown in Figure 1 BK, the substrate (1) is formed by forming a thermal oxide film (3) on a silicon substrate (2) to a thickness of 5000A in an oxidizing atmosphere at a temperature of 950°C, and then applying chemical vapor deposition to this film. After forming a polycrystalline silicon layer (4) to a thickness of 5,000 A at a temperature of 610'C by the (OVD) method, a silicon oxide film (5) with a thickness of 2)tm by the OVD method and a silicon layer by the OVD method. Nitriding 11! (6) is provided. As shown in FIG. 1A, this substrate (1) is heated and maintained at a temperature of 1200° C. from the bottom using a strip heater (7).

そして、上部から直径２〜５ｍｍの線状ヒータ（８）を
基体試料（１）の上面から１〜２ｎｏｎ程度離し、２ｍ
ｍ／秒程度の速度で走査しながら加熱することによって
、線状の溶融ゾーン（９）を多結晶シリコン層（４）内
に得て、これを移動させて再結晶層を得るのである。Then, a linear heater (8) with a diameter of 2 to 5 mm is placed from the top of the base sample (1) at a distance of about 1 to 2 non from the top surface of the base sample (1).
By heating while scanning at a speed of about m/sec, a linear melting zone (9) is obtained in the polycrystalline silicon layer (4), which is moved to obtain a recrystallized layer.

しかし、この方法で得られた再結晶化半導体層は、非常
に大きな単結晶粒からなるものの、若干の制御できない
結晶粒界の発生と、微視的にみれば、小傾角粒界と呼ば
れる結晶粒界が多数発生しているととが知られている。However, although the recrystallized semiconductor layer obtained by this method consists of very large single crystal grains, there are some uncontrollable grain boundaries and, microscopically, crystal grains called low-angle grain boundaries. It is known that many grain boundaries occur.

この原因は多結晶シリコン層（４）の厚さ０．５．ｇｍ
Ｋ比して線状ヒータ（８）による溶融ゾーン（９）の幅
が１−２．＋ｎｍもあって広く、実際には厚さに比べて
無限大の広さの部分が溶融して液相状態になるととＫあ
る。従って、多結晶層中の不純物の不均一分布や、溶融
ゾーン（９）中の微小な熱的ゆらぎが固化速度、方向に
影響を与え均一な結晶成長を妨げているのである。This is because the thickness of the polycrystalline silicon layer (4) is 0.5. gm
Compared to K, the width of the melting zone (9) by the linear heater (8) is 1-2. +nm, which is wide, and in reality, an infinitely large area compared to the thickness melts and becomes a liquid phase. Therefore, non-uniform distribution of impurities in the polycrystalline layer and minute thermal fluctuations in the melting zone (9) affect the solidification rate and direction and hinder uniform crystal growth.

これを避けるために、あらかじめ多結晶シリコン層（４
）に島状にパターニングしたシ、熱酸化膜（３）を部分
的に除去してシリコン基板（１）による種結晶成長が試
みられてはいる。しかし、これらの方法によっても、あ
らゆる形状のパターンで同一品質の単結晶層が得られる
という段階には達していす。To avoid this, a polycrystalline silicon layer (4
), seed crystal growth using a silicon substrate (1) has been attempted by partially removing the thermal oxide film (3) patterned into an island shape. However, even with these methods, we have reached the stage where single-crystal layers of the same quality can be obtained with patterns of any shape.

前記結晶粒界の発生位置を制御することＦｉまだできな
い。It is not yet possible to control the position where the grain boundaries occur.

〔発明の概要〕[Summary of the invention]

この発明は以上のような点に鑑みてなされたもので、単
結晶化すべき多結晶半導体層の上面から線状に加熱輻射
線を照射して溶融させ、その部位を走査移動させるよう
にするとともにその半導体層の上の一部への加熱輻射線
を反射する反射層を設けることによって、半導体層中に
所望の熱分布を形成し、所望の領域の単結晶化が可能な
方法を提供するものである。The present invention has been made in view of the above points, and includes heating radiation irradiated linearly from the top surface of a polycrystalline semiconductor layer to be made into a single crystal to melt the layer, and scanningly move that portion. To provide a method in which a desired heat distribution is formed in a semiconductor layer by providing a reflective layer that reflects heating radiation to a part of the semiconductor layer, thereby making it possible to form a single crystal in a desired region. It is.

〔発明の実施例〕[Embodiments of the invention]

＠２図はこの発明の一実施例における基体試料を示し、
第２図Ａはその平面図、第２図Ｂは断面図である。従来
例と同一符号は同等部分を示す。@Figure 2 shows a substrate sample in one embodiment of this invention,
FIG. 2A is a plan view thereof, and FIG. 2B is a sectional view thereof. The same symbols as in the conventional example indicate equivalent parts.

この基体試料（１ａ）は、シリコン単結晶基板（２）の
上に、これを温度９５０℃で熱酸化してｌ）ｔｍの厚さ
の熱酸化膜（３）を形成し、その上にＯＶＤ法でｍ度６
１０℃で多結晶シリコン層（４）を形成し、そして、そ
の上にいずれもＯＶＤ法で厚さ１００人の第１のシリコ
ン酸化膜（５）および厚さ１００７！１の第１のシリコ
ン窒化膜（６）を順次形成し、ついで、更にその上にス
パッタリングで厚さ４０００Ａでストライプ状にパター
ン化されたモリブデン層００を形成した後、このモリブ
デン層（１（ｌを包み込むように厚さ２）１ｍの＠２の
シリコン酸化膜Ｑｌ）および更にその上に厚さ１０００
人の第２のシリコン窒化膜（２）をＯＶＤ法で順次形成
しである。第２のシリコン酸化膜（ロ）および第２のシ
リコン窒化膜０埴は多結晶シリコン層（４）が溶融した
ときに剥離しないように保唖する。また、第１のシリコ
ン酸化膜（５）は多結晶シリコン層（４）の溶融時その
結晶性を良好に保つ役割を担ったもので、恰２のシリコ
ン酸化膜０１）に比して高温、低圧のＯＶＤ法で形成さ
れるか、または熱酸化膜であって。This base sample (1a) is made by thermally oxidizing a silicon single crystal substrate (2) at a temperature of 950°C to form a thermal oxide film (3) with a thickness of l)tm, and then depositing an OVD film on it. m degree 6
A polycrystalline silicon layer (4) is formed at 10° C., and a first silicon oxide film (5) with a thickness of 100 μm and a first silicon nitride film with a thickness of 100 μm are deposited on the polycrystalline silicon layer (4) using the OVD method. After sequentially forming films (6), and then forming a molybdenum layer 00 patterned in stripes with a thickness of 4000 Å on it by sputtering, a layer of molybdenum 00 with a thickness of 2 ) 1 m @2 silicon oxide film Ql) and a 1000 m thick silicon oxide film Ql)
A second silicon nitride film (2) is sequentially formed using the OVD method. The second silicon oxide film (b) and the second silicon nitride film protect the polycrystalline silicon layer (4) from peeling off when it is melted. Furthermore, the first silicon oxide film (5) plays a role in maintaining good crystallinity of the polycrystalline silicon layer (4) when it is melted, and is heated at a higher temperature than the second silicon oxide film (01). It is formed by a low-pressure OVD method or is a thermal oxide film.

多結晶シリコン層（４）との間に良好な界面特性を有す
るようにする。また、第１のシリコン窒化膜（６）は表
面の平坦化を保持する働きをする。この実施例における
モリブデン層００のパターンサイズは幅５〜５０μｍＫ
対して間隔１０〜１００／ｌので任意に設定してよい。It is made to have good interfacial characteristics with the polycrystalline silicon layer (4). Further, the first silicon nitride film (6) functions to maintain the flattening of the surface. The pattern size of the molybdenum layer 00 in this example is 5 to 50 μm wide.
On the other hand, the interval is 10 to 100/l, so it may be set arbitrarily.

第３図はこの実施例に用いるゾーンメルティング装置の
構成を示す斜視図で、α罎はキセノン（Ｗｅ）ロングア
ークランプ、０４は反射鏡である。第２図に示したよう
な試料基体（ｌａ）にこのような装置を用いて第３図に
一点鎖線矢印りで示すように、Ｘθロングアークランプ
光を線状に集光して照射し。FIG. 3 is a perspective view showing the configuration of the zone melting apparatus used in this embodiment, where α is a xenon (We) long arc lamp and 04 is a reflecting mirror. Using such an apparatus, a sample substrate (la) as shown in FIG. 2 is irradiated with Xθ long arc lamp light by condensing it linearly as shown by the dashed-dotted line arrow in FIG.

線状の溶融ゾーン（９）を生じさせながら、破線矢印Ｍ
のよう〈走査して多結晶シリコン層（４）を単結晶化す
る。但しこの走査Ｍの方向はこの試料基体（］Ａ）の場
合、第２図で説明したモリブデン層ａＯのストライプ状
パターンの方向と平行忙する。While creating a linear melting zone (9), the dashed arrow M
The polycrystalline silicon layer (4) is made into a single crystal by scanning. However, in the case of this sample substrate (A), the direction of this scanning M is parallel to the direction of the striped pattern of the molybdenum layer aO explained in FIG.

このようにすると、試料基体（ｌａ　）の表面はＸｅロ
ングアークランプａ３からの光りによって照射されて加
熱され、昇温した多結晶シリコン層（４）　Ｆｉ溶融し
、光りの収束幅に対応した溶融ゾーン（９）を生じるが
、モリブデン層０υの存在する領域では、光りが反射さ
れるので、加熱の度合が他の領域より低く、従って、他
の領域が十分メルティングポイントを越える温度に昇温
され、多結晶シリコン層（４）における溶融幅が２〜３
ｍｍになっても、この領域では比較的温度が低く、極く
狭い溶融領域しか生じないことになる。従って、固化に
よる再結晶はとの領域から生じ、モリブデンｌ１Ｑｄの
存在していない領域へと及んで行くことになる。このと
き。In this way, the surface of the sample substrate (la) is irradiated and heated by the light from the Xe long arc lamp a3, and the heated polycrystalline silicon layer (4) is melted, resulting in melting corresponding to the convergence width of the light. Zone (9) is generated, but in the region where the molybdenum layer 0υ exists, the degree of heating is lower than in other regions because the light is reflected, and therefore the temperature of the other regions is raised to a temperature that is sufficiently above the melting point. The melting width in the polycrystalline silicon layer (4) is 2 to 3.
mm, the temperature in this region is relatively low and only a very narrow melting region occurs. Therefore, recrystallization due to solidification occurs from this region and extends to the region where molybdenum 11Qd does not exist. At this time.

隣り合うモリブデン層ＱＯの下からも結晶成長が開始さ
れており、それぞれの結晶は中央で出会い、第４図にα
Ｑとして示すような結晶粒界を形成しながＣ）、Ｘｅロ
ングアークランプ（至）による走査に従りて連続的に成
長して大面積単結晶層が得られるのである。Crystal growth also starts from below the adjacent molybdenum layer QO, and each crystal meets in the center, and α
While forming grain boundaries as shown by Q), a large-area single crystal layer is obtained by growing continuously according to scanning by a Xe long arc lamp (C).

上記栴１の実施例では帯状のモリブデン層００を設けた
が＠５図に示す第２の実施例のように任意の微小な形状
にパターニングされたモリブデン層（１０ａ）、（ｌｏ
ｂ）を用いても、そのパターンの中央部から結晶成長が
開始され１周辺部へ及ぶので、このモリブデン層（ｘｏ
ａ）、（ｘｏｂ）の下は単結晶とすることができる。In the example of the above-mentioned Sakai 1, a band-shaped molybdenum layer 00 was provided, but as in the second example shown in Figure @5, the molybdenum layers (10a), (lo
Even when using b), crystal growth starts from the center of the pattern and extends to the periphery, so this molybdenum layer (xo
The portions below a) and (xob) can be made of single crystal.

なお、各実施例とも遮光パターンにモリブデン層を用い
たがその他の高融点金属層またはそのシリサイド層を用
いてもよく、更に、この層はシリコン多結晶層と厚い絶
縁物層との間に設けたが原理的には最上層に設けてもよ
いことは明白である。Although a molybdenum layer is used for the light-shielding pattern in each of the examples, other high-melting point metal layers or their silicide layers may also be used.Furthermore, this layer may be provided between the silicon polycrystal layer and the thick insulating layer However, it is clear that in principle it may be provided on the top layer.

また、実施例では上方からの線状加熱源にＸｅロングア
ークランプを用いたが、レーザ光などのその他の光源、
ヒータ、電子ビーム源を用いてもよく、略３図忙は図示
を省略したが、試料基体の下面からは＠１図に示したよ
うにヒータなどで均一に加熱した方がよいことは勿論で
ある。なお、この発明の対象とする半導体はシリコンに
限るものでないこともいうまでもない。In addition, although a Xe long arc lamp was used as the linear heating source from above in the example, other light sources such as laser light, etc.
A heater or an electron beam source may be used, and although the illustration in Figure 3 is omitted, it is of course better to uniformly heat the sample substrate from the bottom surface with a heater as shown in Figure 1. be. It goes without saying that the semiconductor to which this invention is applied is not limited to silicon.

〔発明の効果〕〔Effect of the invention〕

以上説明したようＫ、この発明では、絶縁物層の上に形
成された多結晶または非晶質の半導体層を有する試料基
体上から線状の加熱輻射線を照射し上記半導体層を溶融
させ、その位置を走査移動させて、単結晶化するに当っ
て、その試料基体の上記半導体層より上部にその上面の
一部を覆う反射層を設けたので、これＫよる温変分布制
御によって単結晶成長領域を精度よく得ることができる
。As explained above, in this invention, linear heating radiation is irradiated from above a sample substrate having a polycrystalline or amorphous semiconductor layer formed on an insulating layer to melt the semiconductor layer, When scanning and moving the position to form a single crystal, a reflective layer covering a part of the upper surface of the sample substrate was provided above the semiconductor layer. The growth area can be obtained with high precision.

【図面の簡単な説明】[Brief explanation of drawings]

＠１図人は従来の単結晶成長方法を示す斜視図。 第１図Ｂはこれに用いる試料基体の構造を示す断面図、
第２図はこの発明の一実施例における試料基体を示し、
第２図Ａはその平面図、第２図Ｂは断面図、＠３図はこ
の実施例に用いるゾーンメルチインク装置を示す斜視図
、拵４図はこの実施例において試料基体内での結晶粒界
の発生状況を示し、第４図ムはその平面図、ＩＩＩ！４
図Ｂは断面図、略５図はこの発明の他の実施例における
試料基体を示し、箔５図人けその平面図、第５図Ｂは断
面図である。 図において、、（ｌａ）ｌ（ｌｂ）は試料基体、（２）
は半導体基板、（３）は絶縁物層、（４）は多結晶半導
体層、（５）は第１のシリコン酸化膜、（６）は第１の
シリコン窒化膜、　（＋ｏ　、（１ｏａ）、（１ｏｂ）
は反射層、ａＳは第２のシリコン酸化膜、０８１は第２
のシリコン窒化膜、Ｑ］はＸｅロングアークランプ、　
（１９は結晶粒界である。 なお、図中同一符号は同一または相当部分を示す。 代理人　大岩増雄 第１図　□ 第２図 第４図Figure 1 is a perspective view showing the conventional single crystal growth method. FIG. 1B is a sectional view showing the structure of the sample substrate used for this,
FIG. 2 shows a sample substrate in an embodiment of the present invention,
Figure 2A is a plan view, Figure 2B is a sectional view, Figure 3 is a perspective view showing the zone melt ink device used in this example, and Figure 4 shows the crystal grains within the sample substrate in this example. Figure 4 shows the state of occurrence of the field, and Figure 4 is its plan view. 4
Figure B is a sectional view, approximately Figure 5 shows a sample substrate in another embodiment of the present invention, Figure 5 is a plan view of the foil, and Figure 5B is a sectional view. In the figure, (la) l (lb) is the sample substrate, (2)
is a semiconductor substrate, (3) is an insulator layer, (4) is a polycrystalline semiconductor layer, (5) is a first silicon oxide film, (6) is a first silicon nitride film, (+o, (1oa), (1ob)
081 is the reflective layer, aS is the second silicon oxide film, and 081 is the second silicon oxide film.
silicon nitride film, Q] is a Xe long arc lamp,
(19 is a grain boundary. In addition, the same reference numerals in the figure indicate the same or corresponding parts. Agent Masuo Oiwa Figure 1 □ Figure 2 Figure 4

Claims (1)

【特許請求の範囲】 （１）絶縁物層上に形成された多結晶または非晶質の半
導体層を有し、この半導体層の上面に絶縁物膜が形成さ
れた試料基体を下面から均一に加熱し、上面からは線状
に加熱輻射線を照射して、当該照射部位の上記半導体層
を溶融させ、その部位を走査移動させて単結晶化する忙
際して、上記絶縁物膜上の一部を覆い高融点材料からな
る所要パターンの反射層を設けることによって上記反射
層の位置、形状によってその発生位置を制御された結晶
粒界に囲まれた半導体単結晶層を得ることを特徴とする
半導体単結晶層の製造方法。 （２）　半導体層はシリコンからなり、絶縁膜はシリコ
ン酸化膜とシリコン窒化膜との２層構造とすることを特
徴とする特許請求の範囲第１項記載の半導体単結晶層の
製造方法。 を館　轟道仕層のトＦＭＩ／ｒ渡虜ナス談鋳物随には互
いに重ねて形成された第１および第２の絶縁物膜を設は
反射層は上記蛤ｌおよび蛤２の絶縁物膜の間に形成する
ことを特徴とする特許請求の範囲第１項記載の半導体単
結晶層の製造方法。 ア （４）　第１および第２の絶縁物膜李いずれもシリコン
酸化膜とシリコン窒化膜との２層構造とすることを特徴
とする特許請求の範囲第３項記載の半導体単結晶層の製
造方法。 （５）　反射層を高融点金属で形成することを特徴とす
る特許請求の範囲第１項ないし第４項のいずれかに記載
の半導体単結晶層の製造方法。 （６１反射層を高融点金属のシリサイドで形成すること
を特徴とする特許請求の範囲第１項ないしｆｔＪ４項の
いずれかに記載の半導体単結晶層の製造方法。 （７）半導体層の下地となる絶縁物層は半導体基板上に
形成することを特徴とする特許請求の範囲館１項ないし
、第６項のいずれか忙記載の半導体単結晶層の製造方法
。 （８）半導体層の下地となる絶縁物層は石英基板で１ｌ
ｌｌｌｉｌｔすることを特徴とする特許請求の範囲第１
項ないし第６項のいずれかに記載の半導体単結晶層の製
造方法。 （９）　加熱輻射線に強力なランプ光を用いる仁とを特
徴とする特許請求の範囲第１項ないし第８項のいずれか
に記載の半導体単結晶層の製造方法。 ００　加熱輻射線にレーザ光を用いるヒとを特徴とする
特許請求の範囲第１項ないし第８項のいずれかに記載の
半導体単結晶層の製造方法。 α９　加熱輻射線に電子ビームを用いることを特徴とす
る特許請求の範囲第１項ないし、第８項のいずれかに記
載の半導体単結晶層の製造方法。[Scope of Claims] (1) A sample substrate having a polycrystalline or amorphous semiconductor layer formed on an insulating layer and an insulating film formed on the upper surface of the semiconductor layer is uniformly removed from the bottom surface. The semiconductor layer on the insulating film is heated, irradiated with linear heating radiation from the top surface, melts the semiconductor layer at the irradiated area, and scans and moves that area to form a single crystal. A semiconductor single crystal layer surrounded by crystal grain boundaries whose occurrence position is controlled by the position and shape of the reflective layer is obtained by covering a part of the layer and providing a reflective layer of a desired pattern made of a high melting point material. A method for manufacturing a semiconductor single crystal layer. (2) The method for manufacturing a semiconductor single crystal layer according to claim 1, wherein the semiconductor layer is made of silicon, and the insulating film has a two-layer structure of a silicon oxide film and a silicon nitride film. The first and second insulating films formed on top of each other are formed on the castings of the FMI/r POWs in the building of Todorodo. 2. The method of manufacturing a semiconductor single crystal layer according to claim 1, wherein the semiconductor single crystal layer is formed during a period of time. (4) Manufacturing a semiconductor single crystal layer according to claim 3, wherein both the first and second insulating films have a two-layer structure of a silicon oxide film and a silicon nitride film. Method. (5) The method for manufacturing a semiconductor single crystal layer according to any one of claims 1 to 4, wherein the reflective layer is formed of a high-melting point metal. (61) A method for manufacturing a semiconductor single crystal layer according to any one of claims 1 to ftJ4, characterized in that the reflective layer is formed of silicide of a high-melting point metal. (7) The base layer of the semiconductor layer and The method for manufacturing a semiconductor single crystal layer according to any one of Claims 1 to 6, characterized in that the insulating layer is formed on a semiconductor substrate. The insulating layer is 1L on a quartz substrate.
Claim 1 characterized in that
7. The method for manufacturing a semiconductor single crystal layer according to any one of items 6 to 6. (9) A method for manufacturing a semiconductor single crystal layer according to any one of claims 1 to 8, characterized in that the heating radiation uses strong lamp light. 00 The method for manufacturing a semiconductor single crystal layer according to any one of claims 1 to 8, characterized in that a laser beam is used as the heating radiation. α9 The method for manufacturing a semiconductor single crystal layer according to any one of claims 1 to 8, characterized in that an electron beam is used as the heating radiation.
JP59016220A 1984-01-30 1984-01-30 Manufacture of semiconductor single crystal layer Pending JPS60160114A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59016220A JPS60160114A (en) 1984-01-30 1984-01-30 Manufacture of semiconductor single crystal layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59016220A JPS60160114A (en) 1984-01-30 1984-01-30 Manufacture of semiconductor single crystal layer

Publications (1)

Publication Number Publication Date
JPS60160114A true JPS60160114A (en) 1985-08-21

Family

ID=11910443

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59016220A Pending JPS60160114A (en) 1984-01-30 1984-01-30 Manufacture of semiconductor single crystal layer

Country Status (1)

Country Link
JP (1) JPS60160114A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03228324A (en) * 1990-02-02 1991-10-09 Mitsubishi Electric Corp Growth of thin polycrystalline si film

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03228324A (en) * 1990-02-02 1991-10-09 Mitsubishi Electric Corp Growth of thin polycrystalline si film

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