JPH0355975B2 - - Google Patents
Info
- Publication number
- JPH0355975B2 JPH0355975B2 JP56209540A JP20954081A JPH0355975B2 JP H0355975 B2 JPH0355975 B2 JP H0355975B2 JP 56209540 A JP56209540 A JP 56209540A JP 20954081 A JP20954081 A JP 20954081A JP H0355975 B2 JPH0355975 B2 JP H0355975B2
- Authority
- JP
- Japan
- Prior art keywords
- electron beam
- silicon
- silicon layer
- electron
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 229910052710 silicon Inorganic materials 0.000 claims description 27
- 239000010703 silicon Substances 0.000 claims description 27
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 26
- 238000010894 electron beam technology Methods 0.000 claims description 24
- 239000012212 insulator Substances 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 5
- 230000001133 acceleration Effects 0.000 claims description 4
- 238000000137 annealing Methods 0.000 claims description 4
- 238000000034 method Methods 0.000 claims description 4
- 230000001678 irradiating effect Effects 0.000 claims description 2
- 229910021419 crystalline silicon Inorganic materials 0.000 claims 1
- 239000013078 crystal Substances 0.000 description 17
- 239000010410 layer Substances 0.000 description 16
- 238000002425 crystallisation Methods 0.000 description 6
- 230000008025 crystallization Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000007711 solidification Methods 0.000 description 2
- 230000008023 solidification Effects 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/2636—Bombardment with radiation with high-energy radiation for heating, e.g. electron beam heating
Landscapes
- Physics & Mathematics (AREA)
- High Energy & Nuclear Physics (AREA)
- Engineering & Computer Science (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Recrystallisation Techniques (AREA)
Description
【発明の詳細な説明】
(1) 発明の技術分野
本発明は、SOIの単結晶化、特に電子ビームを
用いたSOIの単結晶化技術に係る。DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to SOI single crystallization, particularly SOI single crystallization technology using an electron beam.
(2) 技術の背景
SOI（Silicon on Insulator）は絶縁物（膜）上
のシリコンの略称であり、このシリコン内に形成
された複数の半導体を下地層が絶縁体であること
を利用して容易に分離し、大規模集積化のための
一手段とせんとするものである。(2) Technology background SOI (Silicon on Insulator) is an abbreviation for silicon on an insulator (film), and it is easy to integrate multiple semiconductors formed within this silicon by utilizing the fact that the underlying layer is an insulator. This is intended to be a means for large-scale integration.
しかし、絶縁層上に所望なシリコン単結晶を形
成することは容易ではなく、この技術の利用はい
ま一歩であると共に、今後の開発が望まれてい
る。 However, it is not easy to form a desired silicon single crystal on an insulating layer, and the use of this technology is only a step forward, and further development is desired.
(3) 従来技術と問題点
絶縁物、例えば酸化膜上に慣用のCVD法を用
いてシリコンを蒸着させた場合、得られるシリコ
ンは結晶寸法数百Å程度の多結晶体である。この
多結晶シリコン層に最近脚光を浴びているレーザ
ー、例えば連続発振アルゴンレーザーの光を照射
してアニールした場合、レーザー光の局所的で高
い出力のためにシリコンの溶融固化、即ち再結晶
化が起こり、結晶寸法の拡大をはたすことができ
る。しかし、得られる結晶はやはり多結晶体であ
り、結晶法も数μｍ程度である。(3) Prior Art and Problems When silicon is deposited on an insulator, such as an oxide film, using a conventional CVD method, the silicon obtained is a polycrystalline substance with a crystal size of approximately several hundred Å. When this polycrystalline silicon layer is annealed by irradiating it with light from a laser that has recently been in the spotlight, such as a continuous wave argon laser, the locally high output of the laser light causes the silicon to melt and solidify, that is, recrystallize. occurs and can expand the crystal size. However, the crystals obtained are still polycrystalline, and the crystallization method is also about several μm.
(4) 発明の目的
本発明は、上記のような従来技術の現状に鑑
み、SOIにおけるシリコンの結晶寸法の拡大、さ
らには単結晶化を実現することを目的としてい
る。(4) Purpose of the Invention In view of the current state of the prior art as described above, the present invention aims to increase the crystal size of silicon in SOI and realize single crystallization.
(5) 発明の構成
本発明者らは、こうした目的の下、鋭意研究の
結果、加速電圧の異なる複数の電子ビームを用い
るアニール処理によつて上記目的を達成すること
が可能であることを見い出したものである。(5) Structure of the Invention With these objectives in mind, the present inventors have conducted extensive research and found that it is possible to achieve the above objectives by annealing using multiple electron beams with different acceleration voltages. It is something that
単結晶の成長が、溶融、固化の前後にわたる温
度条牛によつて大きく左右されることは周知であ
る。そして、従来のレーザーアニールでは、瞬間
的な急速加熱・急速冷却という条件が大きな結晶
の成長を阻んでいる。そこで、本発明者らは、シ
リコンの下地層である絶縁物を加熱することによ
つて、シリコンの結晶化過程における温度条件を
単結晶化のために有利な条件に変更することを企
図したものである。その具体的手段として、本発
明では、レーザービームではなく電子ビームを用
いる。レーザービームでは波長に応じて特定の物
質だけを加熱することが可能であるにすぎず、ま
た被加熱層の表面から内側へと経時的に（不均一
に）加熱する不都合があるからである。この点電
子ビームでは加速電圧を変化させれば、所望の深
さにある所望の物質を均一に加熱することが可能
である。 It is well known that the growth of a single crystal is greatly influenced by the temperature conditions before and after melting and solidification. In conventional laser annealing, the conditions of instantaneous rapid heating and rapid cooling hinder the growth of large crystals. Therefore, the present inventors attempted to change the temperature conditions during the crystallization process of silicon to conditions favorable for single crystallization by heating the insulating material that is the underlying layer of silicon. It is. As a specific means for this purpose, the present invention uses an electron beam instead of a laser beam. This is because a laser beam can only heat a specific substance depending on the wavelength, and it also has the disadvantage of heating the layer to be heated inward from the surface over time (non-uniformly). In this respect, with an electron beam, by changing the accelerating voltage, it is possible to uniformly heat a desired substance at a desired depth.
以下、実施例を用いて本発明をさらに詳しく説
明する。 Hereinafter, the present invention will be explained in more detail using Examples.
(6) 発明の実施例
第１図を参照すると、、シリコンウエーハ１上
に酸化膜（SiO2）２が形成されており、この酸
化膜はその上に形成されるシリコン単結晶の結晶
方位を規定するように慣用のマスク手法を用いて
パターニングすることができる。SiO2酸化膜２
の厚さは通常は0.8〜1.0μｍであるが、これに限
定されない。そして、酸化膜２の表面に慣用の
CVD法を用いてシリコン多結晶層３を通常4000
〜5000Å程度蒸着させる。(6) Embodiments of the Invention Referring to FIG. 1, an oxide film (SiO 2 ) 2 is formed on a silicon wafer 1, and this oxide film determines the crystal orientation of the silicon single crystal formed thereon. It can be patterned using conventional mask techniques as specified. SiO 2 oxide film 2
The thickness is usually 0.8 to 1.0 μm, but is not limited thereto. Then, on the surface of the oxide film 2, a conventional
The silicon polycrystalline layer 3 is usually 4000 ml thick using the CVD method.
Deposit about ~5000Å.
こうして形成されたSIOに対して２本の電子ビ
ーム，を照射する。１本は加速電圧を10〜
15KV程度にすることによつて表面のシリコン層
３を加熱し、他の１本は50〜60KV程度にする
ことによつて下地酸化膜２を加熱するように設定
する。これら２本の電子ビームは、例えば、対称
的に配置された電子銃からの２本のビームを試料
上方であたかも一本のビームであるかのように合
流させて試料に照射することも、あるいはほぼ同
じ試料位置に２本の電子ビームを試料に対して異
なる角度を持たせて照射することもできる。この
ときの吸収エネルギーの深度分布を第２図に示し
た。 Two electron beams are irradiated onto the SIO thus formed. One has an accelerating voltage of 10~
The surface silicon layer 3 is heated by applying a voltage of about 15 KV, and the base oxide film 2 is heated by applying a voltage of about 50 to 60 KV to the other one. These two electron beams can be irradiated onto the sample by, for example, combining two beams from symmetrically arranged electron guns above the sample as if they were a single beam, or It is also possible to irradiate two electron beams at substantially the same sample position with different angles relative to the sample. The depth distribution of absorbed energy at this time is shown in Figure 2.
このように単結晶化すべきシリコン多結晶層３
のほかに下地酸化膜２をも加熱すると、電子ビー
ムによつて一度溶融されたシリコンの固化過程が
ゆるやかなものとなるために、再結晶化したシリ
コンは非常に大きな結晶寸法のものとなる。実験
的に、少なくとも数百〜数千μｍの単結晶を得
た。なお、発明の本質上、酸化膜２は上記のパタ
ーンである必要はなく、単純な平面的な膜（層）
であることができる。 In this way, the silicon polycrystalline layer 3 to be made into a single crystal
If the underlying oxide film 2 is also heated, the solidification process of the silicon once melted by the electron beam becomes gradual, so that the recrystallized silicon has a very large crystal size. Experimentally, single crystals of at least several hundred to several thousand micrometers were obtained. Note that, in accordance with the essence of the invention, the oxide film 2 does not need to have the above pattern, but may be a simple planar film (layer).
can be.
次に、第３図を参照すると、シリコンウエーハ
１上に例えば寸法20μ×30μ、厚さ0.8〜1.0μｍの
酸化膜２、そしてその上に厚さ4000〜5000Åのシ
リコン多結晶層３が形成されている。これらの層
の寸法や厚さは所望なデバイスの寸法や厚さによ
つて自由に選択することができる。 Next, referring to FIG. 3, an oxide film 2 with dimensions of, for example, 20 μ x 30 μ and a thickness of 0.8 to 1.0 μm is formed on a silicon wafer 1, and a polycrystalline silicon layer 3 with a thickness of 4000 to 5000 Å is formed thereon. ing. The dimensions and thickness of these layers can be freely selected depending on the desired dimensions and thickness of the device.
そして、本発明の第二の態様では、３本の電子
ビーム，，を使用する。ビームの加速電圧
を中央のビームは10〜15KV、両端のビーム
，は50〜60KVに設定し、即ち、中央のビー
ムは表面のシリコン層３を、両端のビーム，
は下地酸化膜２を加熱するように設定する。そ
して、試料上この３本のビームを平行的に走査す
る。 In a second embodiment of the present invention, three electron beams are used. The acceleration voltage of the beam is set to 10 to 15 KV for the central beam and 50 to 60 KV for the beams at both ends.
is set so that the base oxide film 2 is heated. These three beams are then scanned in parallel over the sample.
こうすることによつて、酸化膜２まで加熱され
た両端部では表面シリコン層３のみが加熱された
中央部よりもビームが去つた後の冷却速度が遅く
なり、第３図における横方向AMA′における温度
分布が第４図の曲線Ｑのようなサドル形となる。
このために、一度熔融した表面シリコン層３は最
初中央の部分Ｍが固化し、その固化領域が両端部
Ａ，A′の方へと次第に拡大してゆき、最終的に
表面シリコン層３は完全な単結晶となる。 By doing this, the cooling rate after the beam leaves is slower at both ends where the oxide film 2 has been heated than at the center where only the surface silicon layer 3 has been heated, and the lateral AMA′ in FIG. The temperature distribution at is saddle-shaped as shown by curve Q in FIG.
For this reason, once the surface silicon layer 3 is melted, the central portion M is first solidified, and the solidified region gradually expands toward both ends A and A', and finally the surface silicon layer 3 is completely solidified. It becomes a single crystal.
これは、従来のように一本のレーザービーム
（又は電子ビーム）のみで表面シリコン層をアニ
ールした場合には、ビームが去つた後の温度分布
が曲線Ｐ（第４図）のようなプロフアイルになる
ので、一度溶融したシリコンは両端部Ａ，A′か
ら固化が起こり中央部に進行し、どうしても中央
付近で結晶成長が害され、単結晶化しないという
不都合が除去されるから可能となつたものであ
る。 This means that when the surface silicon layer is annealed with only one laser beam (or electron beam) as in the past, the temperature distribution after the beam leaves will have a profile like curve P (Figure 4). Therefore, once melted silicon solidifies from both ends A and A' and progresses to the center, this is possible because it eliminates the disadvantage that crystal growth is inevitably impaired near the center and does not become a single crystal. It is something.
なお、ビームのスポツトの寸法は必要であれば
数mmのオーダーのものが得られるとも報告されて
いるので、単結晶化できるシリコンの寸法は３本
の電子ビームによつても相当に大きくすることが
できることは明らかである。 It is also reported that the beam spot size can be on the order of several millimeters if necessary, so the size of the silicon that can be made into a single crystal can be made considerably large even with three electron beams. It is clear that this can be done.
(7) 発明の効果
以上の説明から明らかなように、本発明によつ
てSOIにおいて大きな単結晶を得ることが可能と
なる。それによつてSOIの半導体装置への利用も
前進する。(7) Effects of the invention As is clear from the above explanation, the present invention makes it possible to obtain a large single crystal in SOI. This will also advance the use of SOI in semiconductor devices.
第１図は２本の電子ビームを用いた本発明の一
つのビームアニールを示す概略図、第２図は第１
図における深さ方向の吸収エネルギーの分布図、
第３図は３本の電子ビームを用いた本発明のもう
一つのビームアニールを示む概略図、第４図は第
３図における表面層の横方向の温度分布を示す図
である。
１……シリコンウエーハ、２……絶縁物（酸化
膜）、３……多結晶シリコン層、〜……電子
ビーム。
FIG. 1 is a schematic diagram showing one beam annealing according to the present invention using two electron beams, and FIG.
Distribution diagram of absorbed energy in the depth direction in the figure,
FIG. 3 is a schematic diagram showing another beam annealing according to the present invention using three electron beams, and FIG. 4 is a diagram showing the lateral temperature distribution of the surface layer in FIG. 3. 1... Silicon wafer, 2... Insulator (oxide film), 3... Polycrystalline silicon layer, ~... Electron beam.
Claims (1)
の加速電圧による第１の電子ビームを該多結晶シ
リコン層に照射して該多結晶シリコン層を加熱す
ると共に、該第１の電子ビームが照射される領域
を中心として、その両側の多結晶シリコン層に該
第１の加速電圧より高い第２の加速電圧による第
２の電子ビームを照射しながらこれら３本の電子
ビームを平行的に走査して、 該第１の電子ビームが照射された領域で低く、
該第２の電子ビームが照射された領域で高い温度
分布にせしめ、 これらの電子ビームで溶融されるシリコン層を
該第１の電子ビームが照射される領域から外側へ
向つて冷却させ、該多結晶シリコン層の再結晶化
を行なうことを特徴とする電子ビームアニール方
法。[Claims] 1. A polycrystalline silicon layer is formed on an insulator, and a first
The polycrystalline silicon layer is irradiated with a first electron beam with an accelerating voltage of Scanning these three electron beams in parallel while irradiating the layer with a second electron beam at a second acceleration voltage higher than the first acceleration voltage, the area irradiated with the first electron beam and low,
A high temperature distribution is created in the region irradiated with the second electron beam, and the silicon layer melted by these electron beams is cooled outward from the region irradiated with the first electron beam, so that the silicon layer melted by the electron beams is cooled outward from the region irradiated with the first electron beam. An electron beam annealing method characterized by recrystallizing a crystalline silicon layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20954081A JPS58112323A (en) | 1981-12-26 | 1981-12-26 | Process of annealing by electron beams |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20954081A JPS58112323A (en) | 1981-12-26 | 1981-12-26 | Process of annealing by electron beams |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58112323A JPS58112323A (en) | 1983-07-04 |
| JPH0355975B2 true JPH0355975B2 (en) | 1991-08-27 |
Family
ID=16574492
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20954081A Granted JPS58112323A (en) | 1981-12-26 | 1981-12-26 | Process of annealing by electron beams |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58112323A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59178719A (en) * | 1983-03-30 | 1984-10-11 | Agency Of Ind Science & Technol | Electron beam annealing method and the apparatus therefor |
| JP2542928Y2 (en) * | 1989-10-27 | 1997-07-30 | 日本電気アイシーマイコンシステム株式会社 | Master slice semiconductor device |
| JP2002110688A (en) * | 2000-09-29 | 2002-04-12 | Canon Inc | Thermal processing method of soi, and its manufacturing method |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56142630A (en) * | 1980-04-09 | 1981-11-07 | Fujitsu Ltd | Manufacture of semiconductor device |
-
1981
- 1981-12-26 JP JP20954081A patent/JPS58112323A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56142630A (en) * | 1980-04-09 | 1981-11-07 | Fujitsu Ltd | Manufacture of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58112323A (en) | 1983-07-04 |
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