JPS5833822A - Preparation of semiconductor substrate - Google Patents

Preparation of semiconductor substrate

Info

Publication number
JPS5833822A
JPS5833822A JP56132356A JP13235681A JPS5833822A JP S5833822 A JPS5833822 A JP S5833822A JP 56132356 A JP56132356 A JP 56132356A JP 13235681 A JP13235681 A JP 13235681A JP S5833822 A JPS5833822 A JP S5833822A
Authority
JP
Japan
Prior art keywords
silicon
layer
polycrystalline
substrate
oxide film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56132356A
Other languages
Japanese (ja)
Inventor
Toshiro Isu
井須　俊郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP56132356A priority Critical patent/JPS5833822A/en
Publication of JPS5833822A publication Critical patent/JPS5833822A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02502—Layer structure consisting of two layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02598—Microstructure monocrystalline
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02689—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using particle beams
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02691—Scanning of a beam

Abstract

PURPOSE:To form stable single crystalline Si layer covering the whole area by irradiating light beam or electron beam to the polycrystalline or amorphous Si layer deposited on the silicon nitride film over the whole area. CONSTITUTION:The light beam or electron beam is irradiated to the polycrystalline or amorphous Si layer 3 entirely deposited on the Si nitride film 6 formed on the Si substrate 1 via the Si oxide film 2 formed as the basic layer. Thereby, the adequate region of power of irradiated beam used for stable single- crystallization for the whole area of the Si layer can be extended without disappearance of even a part of Si of the Si layer, because disappearance of silicon of the polycrystalline Si layer 3 can be prevented due to the existence of Si nitride film 6 between the Si oxide film 2 and the polycrystalline Si layer 3.

Description

【発明の詳細な説明】 この発明は、基板上に形成された絶縁体膜上に半導体単
結晶層を形成する方法に関するものである０ この明細書では、基板上に形成された絶縁体膜上に半導
体単結晶層が形成されたものを「半導体基体」と呼ぶ。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for forming a semiconductor single crystal layer on an insulating film formed on a substrate. A semiconductor substrate on which a semiconductor single crystal layer is formed is called a "semiconductor substrate."

半導体装置の動作高速化、高密度化の一方法として、絶
縁体上に素子要素を作成することにより、浮遊容量を減
少させ要素間隔を狭くする方法がある。このためＫは、
絶縁体上に半導体単結晶を形成する必要があるが、その
ための従来の方法の一例として、シリコン酸化膜上に多
結晶シリコンを堆積し、その表面にレーザ装置本しくけ
フラッシュランプからの光線または電子線々どを照射し
て表面層を加熱して、シリコン単結晶層を形成する方法
がある。このような方法によって形成された半導体基体
であるシリコン基体の製作中間工程における断面構造を
第１図に示す。第１図において、ｆｔｌは基板であるシ
リコン基板、（２）はシリコン酸化膜、（３）は多結晶
シリコン層、（４）はレーザ装置、フラッシュランプま
たは電子線源、（５）は光線または電子線からなり多結
晶シリコン層＋３１　Ｋ照射される照射ビーム、（ユｃ
Ｏ）はシリコン基板１１）、シリコン酸化膜（２）およ
び多結晶シリコン層（３）からなる製作中間工程におけ
るシリコン基体である。照射ビーム（５）は通常、光学
的、電気的またｔｉ＆椋的にシリコン基体（１００）内
を走査しシリコン基体（１００）全面を照射する。One method for increasing the operating speed and density of a semiconductor device is to reduce stray capacitance and narrow element spacing by forming element elements on an insulator. For this reason, K is
It is necessary to form a semiconductor single crystal on an insulator, and one conventional method for this purpose is to deposit polycrystalline silicon on a silicon oxide film, and then irradiate the surface with light from a flash lamp or a laser device. There is a method of heating the surface layer by irradiating it with electron beams to form a silicon single crystal layer. FIG. 1 shows a cross-sectional structure of a silicon substrate, which is a semiconductor substrate formed by such a method, at an intermediate manufacturing step. In Figure 1, ftl is a silicon substrate, (2) is a silicon oxide film, (3) is a polycrystalline silicon layer, (4) is a laser device, flash lamp or electron beam source, and (5) is a light beam or An irradiation beam consisting of an electron beam and irradiating a polycrystalline silicon layer +31K,
O) is a silicon substrate in an intermediate manufacturing process consisting of a silicon substrate 11), a silicon oxide film (2) and a polycrystalline silicon layer (3). The irradiation beam (5) typically scans the silicon substrate (100) optically, electrically, and/or optically to irradiate the entire surface of the silicon substrate (100).

多結晶シリコン層（３）は照射ビーム（６１を吸収して
加熱される。照射ビーム（６）のパワーがある値よシも
大きければ、多結晶シリコン層（３）は溶融し、照射ビ
ーム（６）の移動または消滅によシ加熱されなくなると
再結晶化が起こる。The polycrystalline silicon layer (3) absorbs the radiation beam (61) and is heated. If the power of the radiation beam (6) is greater than a certain value, the polycrystalline silicon layer (3) melts and absorbs the radiation beam (61). Recrystallization occurs when heating is no longer achieved due to the movement or disappearance of 6).

照射ビーム（５）のパワーが大きすぎると、多結晶シリ
コン層（３）のシリコンが蒸発または飛散して消失して
しまうため、再結晶して単結晶となったシリコン単結晶
層を得るためには、適切な範囲のパワーの照射ビームｉ
ｌｌを使用しなければならない。If the power of the irradiation beam (5) is too large, the silicon in the polycrystalline silicon layer (3) will evaporate or scatter and disappear. is the illumination beam i with power in the appropriate range
ll must be used.

しかしながら、下地のシリコン酸化膜（２）の有無やそ
の膜厚により、照射ビーム（６）の適切なパワーの範囲
が変化するため、下地にシリコン酸化膜（２）の有無や
その膜厚の相違による構造がある場合には、適切なパワ
ーの範囲が狭くなる。最も溶融しにくい部分に対して十
分なパワーを照射した際には、多結晶シリコン層（６）
が部分的に飛散し消失し、また、溶融しやすい部分に適
切なパワーで照射し九際には、溶融しにくい部分は溶融
せずＭ晶化ができないという欠点があった。However, the appropriate power range of the irradiation beam (6) changes depending on the presence or absence of the underlying silicon oxide film (2) and its film thickness. If there is a structure due to this, the range of appropriate power becomes narrower. When sufficient power is irradiated to the part that is most difficult to melt, the polycrystalline silicon layer (6)
There was also a drawback that, when the easily melted parts were irradiated with appropriate power, the hard to melt parts did not melt and M crystallization was not possible.

この発明は、上記の欠点を除去するためになされたもの
であり、基板上に下地のシリコン酸化膜を介して形成さ
れたシリコン窒化膜上に全面的に堆積した多結晶または
非晶質のシリコン層に光線または電子線を照射すること
によって、シリコン層のシリコンが部分的に消失するこ
となく全面にわたって安定して単結晶化シリコン層を得
ることができる照射ビームのパワーの適正値域を広げる
ことができる半導体基体の製作方法を提供することを目
的としたものである。This invention was made to eliminate the above-mentioned drawbacks, and uses polycrystalline or amorphous silicon deposited entirely on a silicon nitride film formed on a substrate with an underlying silicon oxide film interposed therebetween. By irradiating the layer with a light beam or an electron beam, it is possible to widen the appropriate value range of the power of the irradiation beam that can stably obtain a monocrystalline silicon layer over the entire surface without partially dissipating the silicon in the silicon layer. The purpose of this invention is to provide a method for manufacturing a semiconductor substrate that can be manufactured using the following methods.

以下、実施例に基づいてこの発ＴＩＡを説明する。Hereinafter, this originating TIA will be explained based on an example.

第２図はこの発明による半導体基体の製作方法の一実施
例の製作中間工程におけるシリコン基体の断面構造を示
す図である。第２図において、＋１１はシリコン基板、
（２）はシリコン基板（１）の表面部を熱酸化すること
坪よって形成された厚さ約５０００　Ａのシリコン酸化
膜、（６）はシリコン酸化膜（２）上にプラズマＯｖＤ
法により堆積した厚さ約５０ＯＡのシリコン窒化膜、＋
３）ｔ；ｔシリコン窒化膜（６）上に減圧ＯＶＤ法によ
り全面的に形成された厚さ４００ＯＡの多結晶シリコン
Ｎ　、（ｌｏｏａ）　ｈシリコン基板（１）、シリコン
酸化膜（２）、シリコン窒化ｊ［（６１および多結晶ク
リコン層（３）からなるシリコン基体である。FIG. 2 is a diagram showing a cross-sectional structure of a silicon substrate in an intermediate manufacturing step of an embodiment of the method for manufacturing a semiconductor substrate according to the present invention. In Figure 2, +11 is a silicon substrate,
(2) is a silicon oxide film with a thickness of approximately 5000 A formed by thermally oxidizing the surface of the silicon substrate (1), and (6) is a silicon oxide film formed by plasma OvD on the silicon oxide film (2).
A silicon nitride film with a thickness of about 50 OA deposited by
3) t; t Polycrystalline silicon N with a thickness of 400 OA formed entirely on the silicon nitride film (6) by low pressure OVD method, (looa) h Silicon substrate (1), silicon oxide film (2), silicon It is a silicon substrate consisting of nitride (61) and a polycrystalline silicon layer (3).

第１図に示すシリコン基体（１００）の多結晶シリコン
層（３）をビーム径約６０．ｕｍのアルゴンレーザで走
査しながら照射し、走査速度を１０ｃｍ７７ｇとすると
、約１０Ｗのパワーで溶融が起こり、１１ｗで多結晶シ
リコン層（３）の一部のシリコンが消失した。しかし、
第２図に示すシリコン基体（１００１！Ｌ）では、シリ
コン酸化膜（２）と多結晶シリコン層（３）との間にシ
リコン窒化膜（６）が介在するから、第１図の場合と同
一のビーム径および走査速度にしたとき、ｌ。The polycrystalline silicon layer (3) of the silicon substrate (100) shown in FIG. When irradiation was performed while scanning with an um argon laser at a scanning speed of 10 cm and 77 g, melting occurred at a power of about 10 W, and part of the silicon in the polycrystalline silicon layer (3) disappeared at 11 W. but,
In the silicon substrate (1001!L) shown in Fig. 2, the silicon nitride film (6) is interposed between the silicon oxide film (2) and the polycrystalline silicon layer (3), so it is the same as the case in Fig. 1. When the beam diameter and scanning speed are set to l.

Ｗのパワーで溶融が起こり、１２ｗのパワーにおいても
多結晶シリコン層（３）のシリコンの消失を生じない。Melting occurs with the power of W, and silicon in the polycrystalline silicon layer (3) does not disappear even with the power of 12 W.

第３図は第２図を用いて説明した実施例の一応用例の製
作中間工程におけるシリコン基体の断面構造を示す図で
ある。第３図において、第２図と同一符号は第２図忙て
示したものと同様のものを表わしているｏ　（２ａ）は
シリコン基板１１）の表面の所定領域上に形成されたシ
リコン酸化膜、（６ａ）はシリコン基板（１）のシリコ
ン酸化膜（２ａ）が形成されてぃない部分の表面上およ
びシリコン酸化膜（２ａ）の表面上にわたって形成され
たシリコン窒化膜、（１００１））はシリコン基板（１
）、シリコン酸化膜（２ａχシリコン窒化膜（６ａ）お
よび多結晶シリコン層（３）からなるシリコン基体であ
る。FIG. 3 is a diagram showing a cross-sectional structure of a silicon substrate in an intermediate manufacturing step of an application example of the embodiment described using FIG. 2. In FIG. 3, the same reference numerals as in FIG. 2 represent the same parts as those shown in FIG. , (6a) is a silicon nitride film formed on the surface of the part of the silicon substrate (1) where the silicon oxide film (2a) is not formed and over the surface of the silicon oxide film (2a), (1001)) is Silicon substrate (1
), a silicon substrate consisting of a silicon oxide film (2aχ silicon nitride film (6a) and a polycrystalline silicon layer (3)).

第３図に示すシリコン基体（ｘｏ６ｂ）に対しては、左
側の部分の多結晶シリコン層（３）を溶融させるのに、
第２図を用い゛て説明した実施例と同様の条件のアルゴ
ンレーザで１１Ｗのパワーが必要であるので、シリコン
基体（ｌｏｏｂ）に対しては、１１ｗないし１２Ｗのパ
ワーにより、多結晶シリコン層（３）の全面を安定して
再結晶化させてシリコン単結晶層を得ることがで色る。For the silicon substrate (xo6b) shown in FIG. 3, in order to melt the polycrystalline silicon layer (3) on the left side,
Since a power of 11 W is required using an argon laser under the same conditions as in the embodiment described using FIG. 2, a polycrystalline silicon layer (loob) is 3) It is possible to stably recrystallize the entire surface to obtain a silicon single crystal layer.

上記の実施例においては、レーザ光線照射による再結晶
化の場合を示したが、フラッ′シュランプによる光線照
射または電子線照射によって多結晶シリコン層の単結晶
化を行ってもよい。In the above embodiment, the case of recrystallization by laser beam irradiation is shown, but the polycrystalline silicon layer may be single-crystallized by light beam irradiation with a flash lamp or electron beam irradiation.

また、上記の実施例では、減圧ＯＶＤ法によって生成さ
せた多結晶シリコン層を単結晶化させる場合について述
べたが、常圧ＯＶＤ法で生成させた多結晶または非晶質
のシリコン層を用いても、同様に単結晶化することがで
きる。Further, in the above embodiment, a case was described in which a polycrystalline silicon layer produced by a low pressure OVD method was made into a single crystal, but a polycrystalline or amorphous silicon layer produced by a normal pressure OVD method was used. can also be made into a single crystal in the same way.

以上詳述したように、この発明による半導体基体の製作
方法においては、基板上にシリコン酸化膜を介して形成
されたシリコン゛窒化膜上に全面的に形成された多結晶
または非晶質のシリコン層に光線または電子線を照射し
て単結晶化させるので、シリコン層のシリコンの一部が
消失するようなことなくシリコン層の全面にわたって安
定化して単結晶化させることができるための照射ビーム
のパワーの適正値域を広げることができる。As detailed above, in the method for manufacturing a semiconductor substrate according to the present invention, polycrystalline or amorphous silicon is formed entirely on a silicon nitride film formed on the substrate via a silicon oxide film. Since the layer is irradiated with a light beam or an electron beam to form a single crystal, the irradiation beam is used to stabilize and form a single crystal over the entire surface of the silicon layer without causing part of the silicon to disappear. The appropriate range of power can be expanded.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来の半導体基体の製作方法の製作中間工程に
おけるシリコン基体の断面構造を示す図、第２図はこの
発明による半導体基体の裏作方法の一実施例の製作中間
工程におけるシリコン基体の断面構造を示す図、第３図
はこの発明の一応用例の製作中間工程におけるシリコン
基体の断面構造を示す図である。 図において、（１）はシリコン基板（基板）　、（２１
。 （２ａ）はシリコン酸化膜、（３１Ｆｉ多結晶シリコン
層（シリコン層）　、＋６１　、　（６ａ）はシリコ７
窒化膜、（１００）、　（ｌｏｏａ）、　（１００ｂ）
はシリコン基体である。 なお、図中同一符号はそれぞれ同一または相当部分を示
す。FIG. 1 is a diagram showing a cross-sectional structure of a silicon substrate in an intermediate manufacturing step of a conventional semiconductor substrate manufacturing method, and FIG. 2 is a cross-sectional view of a silicon substrate in an intermediate manufacturing step of an embodiment of a semiconductor substrate back manufacturing method according to the present invention. FIG. 3 is a diagram showing a cross-sectional structure of a silicon substrate in an intermediate manufacturing step of an application example of the present invention. In the figure, (1) is a silicon substrate (substrate), (21
. (2a) is silicon oxide film, (31Fi polycrystalline silicon layer (silicon layer), +61, (6a) is silicon 7
Nitride film, (100), (looa), (100b)
is a silicon substrate. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

【特許請求の範囲】[Claims] ＋１１　　基板上にシリコン酸化膜を介して形成された
シリコン窒化膜上に全面的に形成された多結晶または非
晶質のシリコン層に光線または電子線を照射して上記シ
リコン層を単結晶化させることを特徴とする半導体基体
の製作方法。+11 A polycrystalline or amorphous silicon layer formed entirely on a silicon nitride film formed on a substrate via a silicon oxide film is irradiated with a light beam or an electron beam to make the silicon layer into a single crystal. A method for manufacturing a semiconductor substrate, characterized in that:
JP56132356A 1981-08-21 1981-08-21 Preparation of semiconductor substrate Pending JPS5833822A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56132356A JPS5833822A (en) 1981-08-21 1981-08-21 Preparation of semiconductor substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56132356A JPS5833822A (en) 1981-08-21 1981-08-21 Preparation of semiconductor substrate

Publications (1)

Publication Number Publication Date
JPS5833822A true JPS5833822A (en) 1983-02-28

Family

ID=15079441

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56132356A Pending JPS5833822A (en) 1981-08-21 1981-08-21 Preparation of semiconductor substrate

Country Status (1)

Country Link
JP (1) JPS5833822A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01162320A (en) * 1987-12-19 1989-06-26 Agency Of Ind Science & Technol Formation of semiconductor thin film
US5843225A (en) * 1993-02-03 1998-12-01 Semiconductor Energy Laboratory Co., Ltd. Process for fabricating semiconductor and process for fabricating semiconductor device
US5915174A (en) * 1994-09-30 1999-06-22 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for producing the same
US5956579A (en) * 1993-02-15 1999-09-21 Semiconductor Energy Laboratory Co., Ltd. Semiconductor, semiconductor device, and method for fabricating the same
US6610142B1 (en) * 1993-02-03 2003-08-26 Semiconductor Energy Laboratory Co., Ltd. Process for fabricating semiconductor and process for fabricating semiconductor device

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
IEDM TECHNICAL DIGEST=1972 *

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01162320A (en) * 1987-12-19 1989-06-26 Agency Of Ind Science & Technol Formation of semiconductor thin film
US5843225A (en) * 1993-02-03 1998-12-01 Semiconductor Energy Laboratory Co., Ltd. Process for fabricating semiconductor and process for fabricating semiconductor device
US6610142B1 (en) * 1993-02-03 2003-08-26 Semiconductor Energy Laboratory Co., Ltd. Process for fabricating semiconductor and process for fabricating semiconductor device
US5956579A (en) * 1993-02-15 1999-09-21 Semiconductor Energy Laboratory Co., Ltd. Semiconductor, semiconductor device, and method for fabricating the same
US5915174A (en) * 1994-09-30 1999-06-22 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for producing the same
US6316789B1 (en) 1994-09-30 2001-11-13 Semiconductor Energy Laboratory Co. Ltd. Semiconductor device and method for producing the same

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