JPS60159958A - デ−タ転送制御回路 - Google Patents

デ−タ転送制御回路

Info

Publication number
JPS60159958A
JPS60159958A JP1487284A JP1487284A JPS60159958A JP S60159958 A JPS60159958 A JP S60159958A JP 1487284 A JP1487284 A JP 1487284A JP 1487284 A JP1487284 A JP 1487284A JP S60159958 A JPS60159958 A JP S60159958A
Authority
JP
Japan
Prior art keywords
data transfer
instruction
program
data
flag
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1487284A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0218746B2 (enrdf_load_stackoverflow
Inventor
Makoto Sato
誠 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP1487284A priority Critical patent/JPS60159958A/ja
Publication of JPS60159958A publication Critical patent/JPS60159958A/ja
Publication of JPH0218746B2 publication Critical patent/JPH0218746B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)
JP1487284A 1984-01-30 1984-01-30 デ−タ転送制御回路 Granted JPS60159958A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1487284A JPS60159958A (ja) 1984-01-30 1984-01-30 デ−タ転送制御回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1487284A JPS60159958A (ja) 1984-01-30 1984-01-30 デ−タ転送制御回路

Publications (2)

Publication Number Publication Date
JPS60159958A true JPS60159958A (ja) 1985-08-21
JPH0218746B2 JPH0218746B2 (enrdf_load_stackoverflow) 1990-04-26

Family

ID=11873104

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1487284A Granted JPS60159958A (ja) 1984-01-30 1984-01-30 デ−タ転送制御回路

Country Status (1)

Country Link
JP (1) JPS60159958A (enrdf_load_stackoverflow)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60218153A (ja) * 1984-04-13 1985-10-31 Oki Electric Ind Co Ltd プロセッサ間通信方法
JPH03156558A (ja) * 1989-11-14 1991-07-04 Nec Home Electron Ltd ホストｃｐｕとコプロセッサとの間の通信方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60218153A (ja) * 1984-04-13 1985-10-31 Oki Electric Ind Co Ltd プロセッサ間通信方法
JPH03156558A (ja) * 1989-11-14 1991-07-04 Nec Home Electron Ltd ホストｃｐｕとコプロセッサとの間の通信方法

Also Published As

Publication number Publication date
JPH0218746B2 (enrdf_load_stackoverflow) 1990-04-26

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Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term