JPS6015979B2 - Main memory access control mechanism - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a main memory access control mechanism, and particularly in electronic computers, etc., where main memory access for input/output operations delays main memory access of a central processing unit, which in turn reduces the performance of the central processing unit. This invention relates to a main memory access control mechanism for avoiding such problems as much as possible.

Access to the main memory of an electronic computer is performed independently from the central processing unit and the input/output channels.

Therefore, access requests to the same main storage device may conflict with each other. Many input/output operations have physical restrictions on their transfer speeds (for example, in magnetic disk drives, if the data transfer speed determined by the recording density and rotational speed is not secured in the channel, so-called data overrun will occur). When access requests overlap, it is common to give priority to requests related to input/output operations.
In a central processing unit that does not preempt instruction words to a large extent, if main memory access is delayed due to input/output operations, the execution of operations is often delayed accordingly. Usually there is some data buffer in the channel part,
Temporary delays in main memory access can be absorbed.

Then, detailed control may be performed such as changing the priority of main memory access requests depending on when there is sufficient buffer space and when there is little buffer space. Although this is employed to effectively handle conflicts between input and output channels, it can also be used to prioritize the demands of the central processing unit when the demands by the channels are low. However, the above method is effective only when requests are made at the same time. In this case, if there is a difference of even one machine cycle, the first request will be accepted regardless of the request priority, and the subsequent request will have to wait one to several machine cycles until the previous main memory operation is completed. Therefore, no great effect can be expected even if efforts are made to control simultaneous requests. SUMMARY OF THE INVENTION An object of the present invention is to provide a main memory access control mechanism that does not delay the operation of a central processing unit when a main memory access request for an input/output operation is not yet very urgent. In the present invention, on the premise that the input/output control unit has a mechanism for issuing at least two types of requests depending on the degree of urgency when accessing the main memory, the central processing unit executes a microprogram that issues an access request. A mechanism that issues a main memory access notice signal based on the value of a specific field of a microprogram executed at an earlier stage, and handles the main memory access request, upon receiving the notice signal, issues a main memory access notice signal based on the value of a specific field of a microprogram executed at an earlier stage. It has a mechanism to suppress

Next, the present invention will be explained in detail with reference to the drawings.

One embodiment of the invention is illustrated in FIGS. 1 and 2. In FIG. 1, parts indicated by reference numerals 63 and 26 are parts related to the present invention, and the other parts schematically show the structure of a conventional microprogram type central processing unit.

In a computer using a microprogram control system, there is a control memory 4 for storing microprograms called a control memory.
After the microinstruction word at the address indicated by the control memory address register 5 that specifies that address is read out and stored in the control data register 6 that holds the microinstruction word,
The arithmetic operation execution device (hereinafter referred to as counterfeiting) 7 is controlled by the pattern.

One microinstruction word in the register 6 is usually separated by several file days, and in this figure the control memory address control field 61 and device 7 are used to determine the control memory address of the next microprogram step. A main memory control field 62 and a main memory access notice field are shown. The control memory address determining circuit is determined based on the values of the field 61, flip-flops/registers (not shown) in the device 7, and external signals (in this figure, the main memory operation completion signal 21 is shown). 8 determines the next address and sets it in the register 5. Note that in this embodiment, the terms "signal line" and "signal content" may be used to mean the same thing. On the other hand, the device 7 operates depending on the pattern of the main memory control field 62, and for example, raises the request signal 22 when accessing the main memory.
A command code 23 and a main memory address 24 are given to the main memory device 1 of FIG.

The read/write data line 25 is a bidirectional data line in this example, and is connected from the device 7 to the main memory 1 during main memory writing.
Data is sent to the main storage device 1 and the data is sent to the Hishi Nao 7 during the drafting operation.

In this embodiment, a 1-bit main memory access notice field 63 is additionally provided in the conventional microinstruction word. When this bit is "1", a main memory access notice signal 26 is issued to the main memory device 1. On the other hand, the connections between the input/output control register, the central processing unit, and the main memory are roughly as shown in FIG.

In FIG. 2, the main memory bank 1 has two trailing ports 74 for access, each connected to the central processing bank 2 and the input/output control device 3. It is assumed that the system is designed so that, in response to main memory access requests simultaneously issued by the central processing unit 2 and the input/output control unit 3, the request from the input/output control unit 3 is accepted first (by follow-up technology). . Signal lines 21 to 1 between the central processing unit 2 and the main storage device 1
25 has the same meaning as the same number in FIG.
There is. The input/output control device 3 further sends a signal 36 (“1”) indicating whether the main memory access request has high priority or low priority.
', high priority is given), and the central processing unit 2 outputs the main memory access notice signal 26 described above.

The logic gate circuit inside the broken line is the part that realizes the present invention, and as is clear from the figure, the request from the input/output control device 3 is of high priority or is sent from the central processing unit 2. It is configured such that the information is transmitted to the main memory device 1 only when neither the advance notice signal nor the main memory access request signal is issued. Even in a device having a structure other than microprogram control, it is possible to incorporate logic for issuing the advance warning signal 26 in the present invention.

In addition, in the present invention, the generation of the notice signal is determined by the designer using which microphone when designing the device or coding the microprogram.

Since we know whether main memory access will be performed in a program step, we can add coding that will issue a warning signal a little before that. The present invention can also be applied to each main storage device in a system using a so-called interleap method using a plurality of main storage devices.

As an example, the effects of the present invention will be considered in relation to a main memory device having a cycle time six times as long as the basic machine cycle.

First, when the present invention is not applied (provided that a function is provided to prioritize main memory access requests from the central processing unit over low-priority input/output main memory access requests):
Assume that the probability that a main memory request is issued due to an input/output operation in a certain machine cycle is 1/K.

Although the value of K cannot be calculated strictly, when the value of K is large,
It can be assumed that a main memory request due to an input/output operation is issued once every K machine cycles on average. If a main memory request is issued by the central processing unit at a certain time (machine cycle), the probability that a request due to an input/output operation will be issued in the previous machine cycle is 1/K, which is shown in Figure 3. Since this corresponds to situation 1, the delay of the central processing unit due to this is 5 machine cycles, and therefore the expected value of this delay is 5/K machine cycles. Furthermore, one more
The expected value of delay due to a request that occurs before a machine cycle is 4/K (this corresponds to situation 2 in Figure 3), and similarly, summing all expected delay values is 1/K+2/K+3/
K+4/K+5/K=15/K.

Therefore, we decided to suppress main memory access requests associated with input/output operations using the advance notice signal of the present invention (assuming that the advance notice signal is issued two machine cycles before the actual access request).
, since the requests associated with input/output operations that cause situations 1 and 2 above are suppressed, the expected value of contention delay associated with main memory access of the central processing unit is 1/K+2/K+3/K=6/
K, and the delay due to contention is halved.

Note that a, b, c, d, and e in each of situations 1 to 5 in FIG. 3 indicate processing delay times for access requests from the central processing unit. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 and 2 are diagrams for explaining an embodiment of the present invention, and FIG. 3 is a diagram for explaining the effects of the present invention.

In FIG. 1 and FIG. 2, 1... Main storage device, 2... Central processing unit, 3... Input/output control device, 4.
...Control memory, 5...Control memory address register, 6...Control data register, 7...
. . . Arithmetic operation execution device, 8 . . . Control storage address determination circuit, 21, 31 . . . Main memory operation completion response line,
22, 32... Main memory access request line, 23, 33
...Main memory command line, 24, 34...
・Main memory address line, 25, 35...Read/write data line, 26...Main memory access notice line, 36...
. . . Request level designation line, 61 . . . Control storage address control field, 62 . . . Main operation control field, 63 . . . Main storage access notice field.

Figure 3 Figure 1 Figure 2

Claims (1)

[Claims] 1. In a mechanism that handles main memory access requests from multiple partial devices in an information processing device such as a computer, a certain partial device can process specific fields of a microprogram that is executed at a stage prior to the microprogram issuing the access request. The apparatus is characterized in that it has means for generating a notice signal according to a value, and the mechanism for handling main memory access requests has means for suppressing a part of main memory access requests from other partial devices when receiving the notice signal. main memory access mechanism.