JPS5425636A - Access control set for main memory access - Google Patents

Access control set for main memory access

Info

Publication number
JPS5425636A
JPS5425636A JP9171277A JP9171277A JPS5425636A JP S5425636 A JPS5425636 A JP S5425636A JP 9171277 A JP9171277 A JP 9171277A JP 9171277 A JP9171277 A JP 9171277A JP S5425636 A JPS5425636 A JP S5425636A
Authority
JP
Japan
Prior art keywords
main memory
memory access
access
control set
access control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9171277A
Other languages
Japanese (ja)
Other versions
JPS6015979B2 (en
Inventor
Hideo Morisue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP9171277A priority Critical patent/JPS6015979B2/en
Publication of JPS5425636A publication Critical patent/JPS5425636A/en
Publication of JPS6015979B2 publication Critical patent/JPS6015979B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control

Abstract

PURPOSE:To operate CPU not delayed in the stage of the main memory access request for the input and output operation not in emergency, by outputting the main memory access prediction signal a little before the main memory access from CPU.
JP9171277A 1977-07-29 1977-07-29 Main memory access control mechanism Expired JPS6015979B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9171277A JPS6015979B2 (en) 1977-07-29 1977-07-29 Main memory access control mechanism

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9171277A JPS6015979B2 (en) 1977-07-29 1977-07-29 Main memory access control mechanism

Publications (2)

Publication Number Publication Date
JPS5425636A true JPS5425636A (en) 1979-02-26
JPS6015979B2 JPS6015979B2 (en) 1985-04-23

Family

ID=14034117

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9171277A Expired JPS6015979B2 (en) 1977-07-29 1977-07-29 Main memory access control mechanism

Country Status (1)

Country Link
JP (1) JPS6015979B2 (en)

Also Published As

Publication number Publication date
JPS6015979B2 (en) 1985-04-23

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