JPS6015964A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To obtain a memory, in which dielectric resistance between a source and a drain in a transistor is sufficiently higher than normal supply voltage and a hot carrier injection phenomenon is ignored, reliability thereon is high and which can be operated at high speed, by adopting a change into low impurity concentration of a drain diffusion layer and a silicide layer on a low impurity concentration region. CONSTITUTION:A side-wall oxide film 17 is left selectively, and a gate oxide film 5 in a region in which a low impurity-concentration drain diffusion layer 18 must be formed is removed. Dichlorosilane and hydrochloric acid are reacted chemically in the vapor phase, and a polycrystalline or amorphous silicon thin- film 21 is deposited selectively on an exposed region in the surface of a silicon substrate 1. Arsenic ions are implanted after the deposition process, and implanted ions are activated through heat treatment in a short time to form the low impurity-concentration drain diffusion layer 18. Platinum is sputtered and evaporated, a PtSi layer 19 is left on the diffusion layer 18 in a self-alignment manner, a W film is deposited on the layer 19, and an electrode for a wiring by Al 10 is formed, thus manufacturing a memory.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor memory device, and particularly to a semiconductor memory device comprising an ultrafine insulated gate type field effect transistor having a gate length of 1 μm or less and a capacitor. The present invention relates to a memory cell structure suitable for high breakdown voltage and high speed.

[Background of the invention]

2. Description of the Related Art As semiconductor storage devices (hereinafter referred to as memories) become highly integrated, there is a demand for miniaturization of capacitors and insulated gate type field effect transistors (hereinafter simply referred to as transistors) that constitute unit bits of memories. 1 and 2 are a plan view and a sectional view showing a unit bit of a memory based on a conventional structure, which is composed of one capacitor and one transistor. In FIG. 2, 1 is a semiconductor substrate, 2 is a filled oxide film, and 3 and 4 are source and drain diffusion regions having a conductivity type opposite to that of the semiconductor substrate 1 and having a high impurity concentration distribution. Reference numeral 5 denotes a gate m-oxide film, and 6 an electrode constituting a capacitance. A single voltage, usually VDD, is applied to this electrode to form an inversion layer 7 on the surface of the semiconductor substrate 1 directly below the electrode 6. Reference numeral 8 denotes a gate electrode of a transistor that controls charging and discharging of charge to the capacitor, and corresponds to a word line of the memory. 9 is a protective insulating film, and 10 is a metal bit line that is perpendicular to the word line and connected to the drain 4 of the transistor.

In the conventional structured memory shown in FIGS. 1 and 2,
In order to improve the degree of integration, it is necessary to miniaturize the gate 8 of the transistor, but as the gate length is shortened, that is, the effective channel length is shortened, the punch-through withstand voltage is extremely reduced, making it impossible to operate with a normal power supply of 5V. It has a drawback that makes it impossible. The above drawback becomes noticeable when the effective channel length is 0.4 μm or less.

Improving the punch-through breakdown voltage can be achieved by increasing the substrate impurity concentration, but on the contrary, the avalanche breakdown voltage decreases,
Improving the source-drain breakdown voltage is difficult.

Furthermore, an increase in the substrate impurity concentration has the disadvantage of reducing mobility due to impurity scattering, which impedes high-speed operation based on miniaturization of transistors.

In order to eliminate the above-mentioned drawbacks, attempts have been made to miniaturize the constituent transistors and to lower the power supply voltage from 5.0 cm to 3.0 cm. However, the above-mentioned reduction in voltage causes a decrease in the amount of charge stored in the capacitor, resulting in a disadvantage of deteriorating the signal-to-noise ratio. Furthermore, it goes without saying that a decrease in operating voltage results in a decrease in operating speed.

An essential drawback of conventionally structured memories due to miniaturization is that the reliability of constituent transistors cannot be ensured. That is, in a microtransistor with a conventional structure, a high electric field is applied near the drain, and electrons or holes accelerated by the electric field are injected into the gate insulating film. This is because a so-called hot carrier phenomenon occurs. Due to the occurrence of the above phenomenon, a fluctuation in the threshold voltage value and a decrease in transfer conductance also occur at the same time.

Another drawback of the conventional structured memory due to miniaturization is that the gate oxide film 5 is also simply thinned when the constituent transistors are miniaturized. That is, making the gate oxide film 5 thinner has the disadvantage that the input/output capacitance between the gate 8 and the north 3 and the drain 4 increases monotonically, resulting in a decrease in operating speed.

[Purpose of the invention]

An object of the present invention is to eliminate the above-mentioned drawbacks of the prior art, and to provide a highly reliable memory in which the withstand voltage between the source and drain of the constituent transistors is sufficiently higher than the normal power supply voltage, and the hot carrier injection phenomenon is ignored. It's about doing. Another object of the present invention is to provide a memory that can operate at high speed without increasing the input/output capacity.

[Summary of the invention]

The present invention makes it possible to increase the breakdown voltage and speed control of an ultrafine transistor with a gate length of 0.5 μm or less by reducing the impurity concentration of the drain diffusion layer and employing a silicide layer on the low impurity concentration region. Based on the findings. That is, lowering the concentration of the drain diffusion layer allows the depletion layer caused by the drain electric field to extend into the drain diffusion layer, thereby improving the punch-through breakdown voltage. In order to achieve the above-mentioned high breakdown voltage, there is no need to increase the impurity concentration of the semiconductor substrate, so it is possible to prevent a decrease in mobility due to impurity scattering, and high-speed movement is possible. These are to ensure ohmic contact between the drain/diffusion layer and to reduce the resistance of the drain diffusion layer.As for ohmic contact between the low impurity concentration diffusion region and the silicide layer, the surface concentration of the low impurity concentration region before forming the silicide layer is 1018 Crn'I. The above is based on the fact that good ohmic contact can be ensured.The above fact is based on the fact that one of the inventors of the present invention
internal of applied physics
), Vol. 53, No. 5, p. 3690 (1982), that is, when a silicide layer is formed, an impurity precipitated layer with a thickness of about 10 nm is formed on the surface of the diffusion layer directly under the silicide layer, and the surface impurity concentration is about 1. It is based on the phenomenon of increasing orders of magnitude.

Source-drain breakdown voltage and hot carrier resistance characteristics of an ultra-fine transistor having a channel length of 90.5 μm or less by a configuration in which a drain high concentration impurity diffusion layer in the conventional technology is replaced by a combination of a low concentration impurity diffusion layer and a silicide layer can be significantly improved. The above-mentioned high breakdown voltage can be achieved regardless of the substrate ratio or the concentration of fine particles. Therefore, high-speed operation based on miniaturization of the transistor is possible without increasing the threshold voltage value or decreasing the transfer conductance.

When the transistor having the above structure is applied to a memory, the source diffusion layer of the transistor directly connected to the capacitor hardly contributes to the improvement in the withstand voltage. Therefore, from the viewpoint of increasing the capacitance, it is desirable that a P''N+ junction be formed in the source region by the high impurity concentration substrate and the high impurity concentration diffusion layer.

In other words, in a memory composed of a transistor having a gate length of 0.5 μm or less, the impurity distribution of the source and drain diffusion layers of the transistor is configured to be different as described above from the viewpoint of high breakdown voltage, high speed, and large capacity. things are desirable. Furthermore, from the viewpoint of increasing the transfer conductance of the transistor, it is desirable that the surface of the semiconductor substrate immediately below the gate sidewall insulating film on the source side also be comprised of a highly concentrated impurity diffusion layer.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in more detail with reference to Examples.

For convenience of explanation, the explanation will be made using drawings, but please note that important parts are shown enlarged.

Embodiment 1 FIGS. 3 to 8 are diagrams showing an embodiment of a semiconductor memory device according to the present invention, in which reference numeral 1 denotes a silicon substrate of P conductivity type with a specific resistance of 1 Ω. After selectively forming a 0.8 μm thick filled oxide film 2 on the surface of the silicon substrate 1 using conventional device isolation technology, a silicon oxide film 11 and a silicon nitride film 12 used for selectively forming the filled oxide film 2 are formed. The surface of the silicon substrate 1 from which a desired region has been selectively removed is exposed.

Thereafter, a silicon oxide film with a thickness of 20 nm is re-formed on the exposed portion of the silicon substrate 1, and a silicon oxide film is formed using an ion implantation method.
Arsenic (AS) ions of 10<16>cm<-2> were implanted to reach the maximum concentration on the surface of the silicon substrate 1. After the activation heat treatment of the implanted ions, boron (B) ions are implanted under conditions such that the surface impurity concentration is 1018 cm-3,
The activation heat treatment was performed again to form an N+ diffusion layer 13 and a P+ diffusion layer 14, respectively, and a P+/N+ junction was formed in a desired region of the silicon substrate 1. Thereafter, the silicon oxide film 11 and silicon nitride film 12 used as masks for ion implantation were completely removed. Next, a clean gate oxide film 5 with a thickness of 20 nm was formed on the silicon substrate 1, and then a thin silicon film 6 with a thickness of 300 nm was deposited by chemical vapor phase reaction. Ordinary method using poc13 as a diffusion source in the silicon thin film mentioned above? After A (P) diffusion was performed to sufficiently reduce the resistance, the first gate electrode 6 was formed by photolithography according to the capacitance configuration pattern of the memory.

Next, the first gate electrode 6 is formed by low-temperature wet thermal oxidation at 700C.
0.2 on the top and on the N+ diffusion layer 13 in the silicon substrate.
A silicon oxide film 15 with a thickness of 5 μm was formed. In the above-mentioned low-temperature wet thermal oxidation, accelerated oxidation was not performed on the surface of the silicon substrate on which N+ diffusion was not performed, and only an oxide film with a thickness of 50 nm was formed. After the above oxidation step, when the 5Qnm oxide film was completely removed, a silicon oxide film 15 with a thickness of approximately 0.2 μm was left in self-alignment on the exposed portions of the first gate electrode 6 and the N″″ diffusion layer 13. . After that, 2 again
A gate oxide film with a thickness of 0 nm was formed on the exposed portion of the silicon substrate 1, and a second silicon thin film was deposited by chemical vapor phase reaction. After the second silicon thin film is subjected to neighbor diffusion to sufficiently lower the resistance, the silicate glass formed on the surface is removed, and the second silicon thin film surface is thermally oxidized to approximately 0.
．． A 3 μm silicon oxide film was formed. Thereafter, the silicon thin film and the silicon oxide film were simultaneously photo-etched according to the word scarlet pattern to form the control gate electrode 8 and the electrode protection film 16. Next, a silicon oxide film 17 having a thickness of 0.3 μm was deposited over the entire surface by a chemical vapor phase reaction using tetraethoxysilane (S i (OC2H5)4). When the above-mentioned deposited film 17 is etched in the direction of the silicon substrate 1 surface and the duty direction by reactive sputter etching, and the silicon oxide film deposited on the flat part is removed, the control gate electrode 8 side wall and filled oxide are removed as shown in FIG. The silicon oxide film 17 was left only on steep sidewalls such as the ends of the film 2. In this state, arsenic ions were implanted into the silicon substrate surface through the oxide film 5 by ion implantation at an acceleration energy of 7 (lKeV). The second condition is the condition where the maximum impurity concentration is achieved on the silicon substrate surface. The amount of arsenic ions was determined under a number of conditions such that the surface impurity and physical density took various values in the range of IX 1017 to 1020cnr-3.After the above ion implantation, activation heat treatment of the implanted ions was performed to reduce the drain level. Although the concentration diffusion layer 18 was formed, the heat treatment time was set according to each surface impurity concentration,
The final junction depth of the drain diffusion layer was set to 0.25 μm. Next, the gate oxide film 5 remaining on the surface of the drain low concentration diffusion layer 18 was removed, and platinum (Pi) with a thickness of 3 Q nm was deposited on the entire surface by sputtering. Next 45
After heat treatment at 0C, platinum 7 is applied to the surface of the drain diffusion layer 18.
A reside (PtSi) layer 19 was formed.

In the above heat treatment, platinum does not react with the silicon oxide film and no silicide layer is formed. Therefore, after the above heat treatment step, if the remaining platinum is removed with aqua regia, l) t
Since the s r + so 19 is not etched by aqua regia, the PTSI layer 19 is left on the drain low concentration diffusion layer 18 in a self-aligned manner. Here, directly under the ptSi layer, there is a precipitated layer of about 10 μm thick having an impurity concentration about one order of magnitude higher than the surface impurity concentration before forming the ptSi layer.
The ninth layer is formed in a consistent manner. Next, tungsten (W) 20 was deposited to a thickness of 50 nm at 400 C by a chemical vapor phase reaction using tungsten hexafluoride (WFa).

In the above chemical vapor phase reaction, hydrogen 1517 mm, tungsten hexafluoride 30 c c /min, and deposition pressure 40
Under the conditions of Pa and a deposition rate of 15 nm/-, W is deposited only on silicon or silicide. Therefore, the W film is deposited on the pt3i layer 19 in a self-aligned manner. The above-mentioned W film is used to prevent the reaction between the silicide and the wiring metal. Thereafter, wiring electrodes made of aluminum (At) 10 were formed according to a desired circuit system, and a memory was manufactured.

Memories with control transistors having effective channel lengths of 0.4 μm and 0.3 μm were manufactured using the above manufacturing process, and their characteristics were compared with conventionally structured memories. Prior to the above characteristic comparison, the source-drain breakdown voltages at zero gate potential of conventional structure single transistors with effective channel lengths of 0.4 .mu.In and 0.3 .mu.In, respectively, were measured and found to be 5 V and 3 .mu.In, respectively. In fact, 0.3μm
A memory with an effective channel length of 0.4 μm will be destroyed if the power supply voltage is increased beyond 3 μm.
Even a memory with an effective channel length of

In the memory based on this example, the surface impurity concentration of the drain low concentration diffusion layer is set to l-018crn-3 to 5×1.
A memory with an effective channel length of 0.4 μm set to 0”cm-3 operated perfectly at a power supply voltage of 5μm, and no fluctuations in threshold voltage or decrease in transfer conductance due to the hot carrier injection phenomenon were observed. .

When we measured the source-drain breakdown voltage at zero gate potential for the transistor in the above memory, we found that the surface impurity concentration of the drain low concentration diffusion layer 18 was 3 x 1.
018cm-3 was the highest, about 9.5cm.

Surface impurity concentration is I X 1”O18, I XlO19
and 6.5, 7.5 and 6.2■ for each transistor of 5×1019Cn1-3, respectively.

When the source-drain breakdown voltage of the transistor at zero gate potential was measured in the memory based on this example, which was constructed of a transistor with an effective channel length of 0.3 μm, it was found that the surface impurity concentration of the drain diffusion layer 18 was I.
The highest value at X 10”cm-3 was 6.2■,
X1018. lXlO19 and 5X1019on
-3 surface impurity concentrations are valleys, 4.8, 4.0
The value was 3.5■. The above memory in which the surface impurity concentration of the drain diffusion layer 18 is I.times.10.sup.18 cm.sup.-3 can be operated with a 5V power supply even though the effective channel length of the transistor is extremely short at 0.3 .mu.m. In the memory based on this example, the surface impurity concentration of the drain diffusion layer]8 is 10'' cm-
In a transistor composed of less than 3 transistors, good ohmic characteristics could not be obtained between the silicide layer 19 and the drain diffusion layer 18, and the memory could not operate.

The operating speed characteristics of the memory cell based on this example were also evaluated. Although the effective channel length of the transistor is 0.4 μm and the surface impurity concentration of the drain diffusion layer 18 is 1018 on-'', the transfer conductance is a conventional structure manufactured using a silicon substrate 1 having an impurity concentration of 1×10'' cm-3. The transfer conductance was approximately 1.3 times that of the transistor, confirming high-speed operation. Furthermore, the transfer conductance of a prototype transistor was measured by configuring the source diffusion layer 13 of the memory transistor in this example so as to have the same impurity distribution as the drain diffusion layer 18. It became about 1.5% smaller than that. From the above results, the impurity distribution of the source/drain diffusion layers in the control transistor of the memory is not the same, and the drain diffusion layer 18 is 5 x 1018 cm, probably from the viewpoint of improving the breakdown voltage.
It has been found that the structure based on this embodiment, which has a low impurity surface concentration of -3 or more and less than 1020 cm -'' and a high impurity surface concentration distribution for the source diffusion layer 13 from the viewpoint of high-speed operation, that is, improvement of transfer conductance, is desirable. Ta.

Embodiment 2 FIGS. 9 and 10 are diagrams showing another embodiment of the present invention. In the first embodiment, after selectively leaving the sidewall oxide film 17, a low impurity VIa drain diffusion layer]8
The goo 11 film 5 in the area where it is to be formed is removed. After that, dichlorosolane (SiI (2Ct2) and hydrochloric acid (HO
The chemical vapor phase reaction of 2) was carried out at a temperature of 775C.
A polycrystalline or amorphous silicon thin film 21 having a thickness of 3 μm was selectively deposited on the exposed surface area of the silicon substrate 1 . The conditions for forming the silicon deposited film are dichloro7tz silane 200cc 7mm, hydrochloric acid 5Q
The conditions were c c 7 mm hydrogen 75 t/mm, and the deposition rate was 10 nm/min. In the deposition of the silicon thin film under the above conditions, unevenness called facets were generated even at the boundary with the sidewall oxide film 17, and a flat shape could be obtained. After the above deposition step, arsenic ions were implanted. The ion implantation conditions for the first part are as described above.
The conditions are the same as those for forming the drain diffusion layer 18 in the embodiment. After that, 1100i1:? A short-time heat treatment was carried out under the conditions of . The diffusion coefficient of impurities in the polycrystalline or amorphous silicon deposited film 21 is JO to 20 times larger than the diffusion coefficient in single crystal silicon. Therefore, due to the above-mentioned short-time heat treatment, the impurity distribution in the silicon deposited film 21 becomes a substantially uniform concentration distribution, and the drain diffusion layer 18 in the silicon substrate 1 is approximately 2.0 m thick from the surface of the silicon substrate 1.
It is formed only to a depth of 0 μm. Note that the source diffusion layer 13 that has already been formed by the above-mentioned short-time heat treatment
The concentration distribution of etc. is hardly affected. After the above-mentioned single-hour heat treatment, platinum was sputter-deposited, and thereafter a memory was manufactured based on the first example.

The source-drain breakdown voltage at zero gate potential was measured for the memory transistor manufactured based on this example. The measured transistor had a gate length on the mask of 0.2 μm, and a surface concentration of the drain low concentration diffusion layer 18 of I x 1018 cm-3 and 5 x 10" cm-3, respectively.
I x 1019 cm-3, 5 x 1019 cm-3. The breakdown voltage of each of the above transistors is 10.5
．． They were 8.0, 7.5 and 6.5■. The reason why the memory transistor according to this embodiment was able to achieve a higher breakdown voltage despite having a shorter gate length than the transistor according to the first embodiment is that the impurity concentration distribution in the drain diffusion layer 18 to which the maximum electric field is applied is Almost uniformly distributed,
This is thought to be because the electric field is distributed almost ideally. Memory case 5 with a gate length of 0.2 μm based on this embodiment
■It was found that it can be operated with a normal power supply and that there is no decrease in reliability due to hot carrier injection. The memory cell having a gate length of 0.2 μm based on this embodiment has a speed increase of about 1.9 times compared to the memory cell using a transistor having an effective channel length of 0.4 μIn based on the first embodiment, that is, the transmission speed of the transistor is increased by about 1.9 times. Conductance was improved. The above result is an extremely revolutionary improvement considering the fact that a memory cell of the same size based on a conventional structure cannot operate without lowering the power supply voltage, so the effective speed increase is not directly proportional to the transistor miniaturization rate. . In this example, the maximum impurity concentration in the source diffusion layer 13 of the memory transistor was configured to match the maximum impurity concentration in the drain diffusion layer 18, and the transfer conductance of the prototype transistor was also measured.
It was about 30% smaller than that of this example. From the above results, it has been found that it is desirable to configure the maximum impurity concentration of the source diffusion layer 13 to 1020 cm''3 or more, as in the conventional structure, from the viewpoint of high-speed operation of the memory.

In the first and second embodiments of the present invention described above, the impurity concentration region necessary for ohmic contact is configured in a self-aligned manner with the ptSi layer by utilizing the effect of impurity precipitation directly under the ptSi layer during formation of the ptSi layer. However, the above ptS
The i-layer is made of Mo, W, pd, and Ni.

It may be replaced with a silicide film made of other high melting point metals such as Ti+'ra, Nb, Cr, and pr, or a mixture thereof. Further, in each of the embodiments described above, an example is shown in which a P''N+ junction is formed in the source diffusion layer, but it is also possible to omit the formation of a P+ layer or even an N4 layer. is the source
Although an example has been shown in which the drain diffusion layer is formed using arsenic ions, the above-mentioned diffusion layer may be formed using arsenic ions, but the method for forming the layer is not limited to ion implantation, and any method may be used as long as it does not depart from the spirit of the present invention. Alternatively, other known methods may be used, such as a thermal diffusion method. Further, in each of the above embodiments, for convenience of explanation, a so-called N-channel transistor is shown in which a P-conductivity type semiconductor substrate 1 is used and source/drain regions are formed by Nm impurities. Needless to say, the present invention can also be applied to so-called P-channel transistors that constitute impurities.

〔Effect of the invention〕

According to the present invention, a semiconductor memory device can be constructed using insulated gate field effect transistors having an extremely short gate length of 0.2 μm, and can be operated with a normal power supply of 5V. According to the present invention, the source-drain breakdown voltage of a transistor can be improved without increasing the semiconductor substrate concentration, and the source diffusion layer directly coupled to the capacitor can be maintained at a high impurity concentration. Therefore, there is an effect that the speed of the semiconductor memory device can be increased in proportion to the rate of miniaturization of the gate length without a drop in the power supply voltage or a decrease in the transfer conductance.

[Brief explanation of the drawing]

1 to 2 are plan views and cross-sectional views of a conventional semiconductor memory device in which a memory cell is composed of one transistor and one capacitor, and FIGS. 3 to 8 show a first embodiment of the present invention. The cross-sectional views shown in FIGS. 9 and 10 are cross-sectional views showing a second embodiment of the present invention. Itz 5 /4 13 6 fJ q mouth 10121

Claims (1)

[Scope of Claims] 1. In a memory cell composed of one insulated gate type field effect transistor that controls a low load storage to one iJj capacitance, the memory cell is connected to the electrical capacitance. The source region of the insulated gate field effect transistor is formed in the semiconductor substrate by an impurity diffusion layer having a conductivity type opposite to that of the semiconductor substrate, and the drain region of the insulated gate field effect transistor is opposite to the semiconductor substrate. It has 4 city types, and its maximum concentration is 1028ffi.
-3 to 10" cm-3 of an impurity diffusion layer and a silicide layer. 2. The semiconductor memory device according to claim 1, wherein the upper six-layer tunnel-in region At least a portion of the semiconductor memory device is configured within a semiconductor thin film deposited on a semiconductor substrate.