JPS60158673A - Manufacture of field-effect transistor - Google Patents

Abstract

PURPOSE:To lower series resistance, and to reduce a short gate effect by implanting ions in order to form a channel layer and shaping a gate electrode through a lift-off while implanting ions in order to form source-drain regions as being separated from the gate electrode. CONSTITUTION:An insulating film 16 is applied on a GaAs substrate 1, and a gate electrode is patterned by a photo-resist film 17. A window for a gate electrode section is bored, and ions are implanted in order to form a channel layer 2' and a metallic film 9 for the gate electrode is applied. The metallic film 9 is lifted off, and the gate electrode 5' is patterned. Ions are implanted 10 in order to shape source-drain regions while being separated from the gate electrode by 0.1-0.3mum. The source-drain regions 3', 4' and the channel layer 2' are connected electrically through annealing in order to activate ion implanting layers. Lastly, source-drain electrodes 6, 7 are formed through a lift-off.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to an integrated circuit for high-speed signal processing, and in particular to an integrated circuit for high-speed signal processing.
The present invention relates to a method for manufacturing an integrated circuit including an MES-FET using a compound semiconductor such as As.

[Background of the invention]

In integrated circuits using compound semiconductors such as GaAs as substrates, M
ES-FETs are used. As shown in FIG. 1, this FET has an n-type channel layer 2, an n+-type source/drain region 3, 4, and a gate electrode formed on each surface, as shown in FIG. 5, source/drain electrodes 6 and 7, and is operated by controlling the current flowing between the source/drain electrodes through the channel layer 2 by an electric field applied from the gate electrode 5.

One of the problems with improving the performance of FETs is that the source and drain resistances increase due to the surface depletion layers 8, 8' in the low concentration regions between the gate electrode and the source/drain regions 3, 4. .

As a means to prevent this problem, the source/drain regions 3 and 4 are formed by self-aligning with respect to the gate electrode 5.
Methods of suppressing the surface depletion layer are being considered. FIG. 2 shows a typical example of a conventional self-line type MES-FET. In this FET, by implanting n4 ions for the source/drain regions 3' and 4' using the heat-resistant gate electrode 5' as a mask, self-alignment of both is achieved, and activation heat treatment after implantation is possible. .

The manufacturing procedure for this device is as shown in FIGS. 3a and 3b. First, ions are implanted to form the channel layer 2', and then a heat-resistant metal 9 such as tungsten is deposited (FIG. 3a). .

Next, using the photoresist film as a mask, electrode 5' is applied to gate 1.
(Fig. 3b). Finally, source/drain electrodes are formed by lift-off (not shown).

In the conventional Self-Line FET manufacturing method described above, dry etching is required when etching the deposited heat-resistant metal film 9 to form the Glue 1 to electrodes. Since the selectivity with respect to the aAs substrate is not very high, the surface portion 11.11' of the GaAs substrate is etched. Therefore, a constriction is formed between the channel layer 2' and the source/drain regions 3' and 4', making it difficult for current to flow and increasing the series resistance. Also.

There were problems such as deviations in the dynamic pressure threshold voltage.

As a method to prevent this, the self-line process shown in FIGS. 4a to 4d has been considered. In this process,
After forming a gate pattern 13 with a photoresist film 12 on the surface of the GaAs, using the resist film 12 as a mask, ions are first implanted to form a channel 2' (
a). Further, a heat-resistant metal 9 is vapor-deposited with the same resist film attached, and lift-off is performed using this resist film to form a gate electrode 5' (b). after that,
Similar to the above conventional method, by ion implantation 10, the source/
After forming the drain region (C) and heat treatment for activation (annealing), source/drain electrodes 6°7 are formed, and the FE
Complete T (d).

In this process, since the gate electrode 5' is patterned by lift-off, the surrounding GaAs surface can be formed without being etched. Here, 14 is a photoresist film for an ion mask.

However, the FET manufactured by the above process has the following structural defects. That is, the source/drain regions 3' and 4' are formed adjacent to the gate electrode 5', and during annealing, the source/drain regions also diffuse into the gate 1 under the electrode, so that a Schottky junction occurs in this part. The reverse breakdown voltage of FET deteriorates, leakage current flows between gate and source, and FET characteristics deteriorate.

To prevent this, N4 ion implantation 10 is performed at high energy (15O-200KeV).

A method has been considered in which the source/drain region is formed deep and the surface carrier concentration in this region is lowered. In this case, when the gate length 15 is 1 μm or less, the two-dimensional effect of the electric field between the source and drain becomes significant, and pinch-off becomes difficult due to the so-called short gate effect, resulting in deterioration of FET characteristics.

Moreover, in this process, after lift-off for gate electrode formation, the Ga As surface 11.11' is still exposed and can be contaminated or damaged during various subsequent processes. This reduces carriers and causes deterioration of FET characteristics.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned drawbacks of conventional self-line type FETs, to provide a FET having a structure with low five-series resistance and little short gate effect, and a manufacturing process thereof.

[Summary of the invention]

In the present invention, ions for forming a channel layer are implanted into the part where the gate electrode is patterned in the insulating film, and then the gate electrode is formed in that part by lift-off, and then the ions for forming the source/drain region are implanted. By performing the implantation at an appropriate distance (0.1 to 0.3 μm) from the gate electrode using Selfa Line technology, and electrically connecting the above region and the channel layer by diffusion during annealing, The above objectives were achieved.

The gist of the present invention will be explained in detail using FIG.

In the FET manufacturing process of the present invention, GaAs-based l7f
#4 all over i1! ! After depositing the edge film 16 and patterning the gate electrode using the photoresist film 17, the insulating film 16 is etched to open a window in the gate electrode portion, and then ions are implanted for forming the channel layer 2' and the gate electrode is patterned. The metal film 9 is sequentially deposited (,).

Next, the metal film 9 is lifted off by dissolving the photoresist film 17, and the gate electrode 5' is patterned (not shown).

Next, 0.1 to 0.3 μm li! from the gate electrode! Then, ion implantation 10 for forming source/drain regions is performed. This distance is adjusted using the Selfa Line technology (b). After that, annealing is performed to activate the ion-implanted layer. By this annealing, the implanted ions are diffused by about 0.2 .mu.In from the broken line 18 to the solid line 19, and the source/drain regions 3', 4' and the channel layer 2' are electrically connected (e).

Finally, source/drain electrodes 6 and 7 are formed by lift-off to complete the FET (d).

In the FET formed by the above process, Ga A s
The surface is protected from the beginning by an insulating film 16 except for the electrode forming portion, and it is possible to avoid FET deterioration factors such as contamination and damage.

Furthermore, since the source/drain regions 3' and 4' can be formed shallowly and at an appropriate distance from the gate electrode 5', the reverse breakdown voltage of the gate electrode is high and the short gate effect is less likely to occur.

[Embodiments of the invention]

Example 1 Below, the manufacturing process of the MES-FET of the first example of the present invention will be explained with reference to FIG.

First, as shown in Figure 6(,), semi-insulating Ga
An insulating film Aj2N16 is deposited on the Ag substrate.

Insulating films include AQN films and SiO□.

Si, N4. SiN based on plus v CV D.

5iON film, GaN, AQz O3 film, etc. can also be used. The film thickness is preferably as thin as possible to completely cover the GaAs surface, and is preferably about 500 to 1000 mm. Approximately 5,000 pieces of #@marginal membrane 20 for a spanner are applied on top of the membrane. This film may be of any material as long as it has etching selectivity with respect to the film 16, and if AQN is used as the underlayer, SiO.

Si3N4 etc. are preferable. After forming these films, a gate electrode is patterned using a photoresist film 17, and using this photoresist film as a mask, the insulating films 20 and 16 are sequentially selectively etched to form a window Lj of the gate electrode portion 21 (
b). Alternatively, the photoresist film 17 may be used as a spacer and the spacer film 20 may be omitted.

Ion implantation 22 for forming the channel layer 2' is performed from this window 21 portion. Si ions are convenient as the ion species, but Se, S, etc. may also be used. The implantation energy is 60KeV in the case of Si, and the density is when the threshold voltage is -1V.
There are 2×1012 CI11-2 (c).

Next, we will introduce tungsten (Vi), which is a heat-resistant gate electrode material.
) Depositing membrane 9 by sputtering. The film thickness is a balance between stress reduction and low resistance.

3,000 to 4,000 people is appropriate. In addition to W, electrode materials include Ta, Hf, Ti-W, Mo-W
, Hf-W, or their nitrides, silicides, etc. (d). Furthermore, the deposition method is not limited to sputtering, but may also be vapor deposition, CVD, or the like.

Next, by dissolving at least one of the photoresist film 17 or the spacer film 20, the gate electrode sputter [9] is lifted on. Then, the gate electrode 5' and the protective film 16 are left on the GaAs surface, and the other films are removed (e). If the spacer 20 is a 5in2 film, it can be dissolved with boiling acid.

Next, a spacer film 2 is formed to separate the source/drain regions 3' and 4' from the gate ff1FA5'.
3. A CV D Sio 2 film is suitable as the film, and the film thickness is 0.1 to 0.31 h m. In this case, the gate electrode side surface portion 24 is also coated isotropically with approximately the same thickness. Further, the height is approximately the same as that of the gate electrode (~0.5 μm), and functions as a mask during ion implantation.

Therefore, when implanting 84 ions for the source/drain region, the gate electrode 5' and its side surface 24 serve as a mask, and the source/drain regions 3', 4' and gate electrode 5' are separated by the thickness of the side surface 24. be done. The ion implantation 10 is performed through the protective film 16 and the spacer film 23, but when the thickness of the spacer 23 is 1 μm or more, the total film thickness exceeds 0.2 μm, so the spacer is anisotropically dry etched. It is necessary to remove part or all of it. This anisotropic etching is performed by reactive ion etching using Freon gas.

Alternatively, the ion implantation 10 may be performed after removing the protective film 16 in the source/drain region. 14 is a photoresist film for masking the portion other than Fl'ET.

The energy of the ion implantation 10 depends on the thickness of the films 16 and 23, but it is the sum of both! 1 if 1 is 0.1 to 0.2 μm
A suitable value is 20 to 200 Kev, and the source/drain regions are formed at a depth of about 0.2 μm from the surface. The implantation density is about 1 to 2 x 10 l3c111-2 uN(f).

Next, the photoresist [14] is removed and annealing is performed to activate the injection layer. The annealing conditions are 800° C. for 20 minutes, during which time the implanted ions are diffused and the source/drain regions 3', 4' and the channel layer 2' are electrically connected (g).

Finally, windows are opened in the photoresist film 25 using source/drain legs, and a metal film 26 for source/drain electrodes is deposited (h). It has been used conventionally as a metal film for source/drain electrodes. Au/Ni/Δu G
A multilayer film consisting of e. The total film thickness is approximately 0.3 μm. Thereafter, the excess metal is lifted off using the resist film 25, and the electrodes 6' and 7' are subjected to heat treatment for alloying, etc., to complete the FET element (not shown).

As described above, a FET 174 is obtained in which the source/drain regions can be formed relatively shallow and separated from the gate electrode, the gate reverse breakdown voltage is high, and the short gate effect is small. Furthermore, from the beginning of the process, the GaAs surface
Until just before each electrode 5', 6', 7' is deposited,
6, it is possible to improve and stabilize the 'li tetrad characteristics.

Embodiment 2 FIG. 7 shows the main part of the manufacturing process of the FET of the second embodiment of the present invention. In this example, instead of the spacer 23 in the process of the previous example, a gate electrode having a T-shaped cross section was used to separate the gate electrode and the source/train region.

The other parts are completely the same as in Example 1, and the explanation will be omitted.

In this embodiment, after the protective film 16 is deposited, about 5000 isotropically etched spacer films 20' are deposited. A plasma SiN film is used as the spacer film 20', and is etched by dry etching using CF4 gas.
Perform μm side etching.

26 is a mask during side etching of the spacer film 20', and S! O, film is suitable, but resist film 17
It is also possible to use both. That is, the membrane 20',
After sequentially depositing 27, a gate electrode is patterned using a photoresist film 17, and using this resist film 17 as a mask, films 27, 20' and 16 are sequentially anisotropically etched, and then film 20' is side-etched. (a).

Next, as in Example 1, a metal for the gate electrode is deposited.
) and lift-off to form Ge-1~ electrodes. Furthermore, after removing the spacer film 20' and mask film 27, ion implantation 10 for source/drain regions ?, /, 4/ is performed using the T-shaped gate/electrode 5'' as a mask (C). After depositing the cap film 28 for annealing, annealing is performed at 800° C. for 20 minutes to activate the −r-on injection layer (d).
It is also possible to substitute 1J16.

Finally, source/train regions are formed in the same manner as in Example 1 to complete rFE '1'.

According to this process, the source/drain region 3' is formed by the length of the cap of the T-shaped gate electrode 5#.

4' and goo 1-electrode 5'' can be separated.

Embodiment 3 FIG. 8 shows the main parts of the process of the third embodiment of the present invention. The feature of this embodiment is that the source/drain electrodes are formed in self-alignment with respect to the gate electrode.
The process before forming the source/drain electrodes is exactly the same as in Example 1. Therefore, the explanation of that part will be omitted.

In this embodiment, after annealing the ion implantations 12', 3', and 4', the spacer film 23 and the protective film 16 are etched by anisotropic dry etching, leaving the side surface portions 24 of the gate electrode. /Open a window for drain electrode formation. After that, the metal film 2 for source/drain electrodes is
6 (a).

Next, the surface of the photoresist 1 is coated flatly with a Ga Ats coating (29), and then removed from the surface by milling. As shown in the figure, the gate electrode 5'
The metal film 26 in this portion is preferentially milled. In this way, only the metal film in the source/drain region is left and the remaining resist film 29 is removed to complete the F E 71' film (C).

〔Effect of the invention〕

As described above in detail with reference to the embodiments, according to the present invention, even when the source/drain regions are formed shallowly, the gate electrode and the source/train regions can be separated, the reverse breakdown voltage is high, and the short gate effect is less likely to occur. We can provide FET.

Further, since the QaAs surface is protected by an insulating film from the beginning of the process, there is no deterioration of device characteristics due to damage or contamination, and the present invention can provide a high-performance and stable FET.

Furthermore, since ion implantation for channel formation is performed after removing the protective insulating film, the Ga As
The channel layer does not wear out due to surface scraping, and the electrical characteristics can be stabilized.

[Brief explanation of drawings]

Figure 1 is a sectional view showing the main structure of the MES-FET, Figure 2
3 is an explanatory diagram of a conventional self-line type FET and its process. FIG. 4 is an explanatory diagram of another conventional self-line type FET. FIG. 5 is an explanatory diagram of the process of the FET of the present invention. Figures 7 and 8 respectively show the first embodiment of the present invention. Second. It is a process explanatory diagram of a 3rd example. 1...GaAs substrate, 2.2'...channel layer, 3°3', 4,4'...source/drain region,
5゜5/, 5 II...gate electrode, 6,6'
, 7, 7' ... 2nd eye 3rd prisoner 4th country 5th eye N li'' Figure 6 Figure 7 Iku δ Figure

Claims (1)

[Claims] 10. A step of patterning a gate electrode with a protective insulating film on the surface, implanting ions for forming a channel layer into the window-opened portion, and further forming a gate electrode in that portion by lift-off. , a step of performing ion implantation for source/drain regions away from a gate electrode. 2. An insulating film is deposited on the side surface of the gate electrode, and ions for source/drain regions are implanted using the side insulating film as a mask to separate the gate electrode from the gate electrode. A method for manufacturing field effect transistors. 3. A patent characterized in that the cross section of the gate electrode is formed into a T-shape, and the source/drain region and the gate electrode are separated by performing ion implantation for forming the source/drain region using the gate electrode as a mask. Field effect 1 according to claim 1 - a method for manufacturing a transistor.