JPS60158640A - Integrated circuit - Google Patents

Abstract

PURPOSE:To enable to execute plural kinds of test modes by inputting voltage signals of plural kinds of levels in one piece of terminal for test by a method wherein A-D converting circuits provided between the terminals for test and a logical circuit are respectively connected to each of the terminals for test and the logical circuit, and a previously prescribed signal is inputted in the logical circuit according to a level of analog voltage, which is impressed on the terminals for test. CONSTITUTION:Integrated circuits 1-3 having terminals T1-T3 for test, wherein signals for executing prescribed test modes are inputted, are provided. Terminals 1a-3a for test are connected to the analog input side of the converting circuits 1-3, while a logical circuit 100a, which is involved in the test, is connected to the digital output side T11-T33 of the A-D converting circuits 1-3. By inputting voltage signal of plural kinds of levels in these terminals T1-T3 for test, the previously prescribed test modes are executed according to the voltage signals.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an integrated circuit equipped with a test input terminal for testing a circuit in a large-scale integrated circuit such as a one-chip microcomputer.

Conventionally, integrated circuit testing involves manually inputting a test signal of "Higl+" level or "LO11 Pa level" to the test terminal provided on the integrated circuit, and checking the logical output that is established in response to this input signal. If the integrated circuit has two test terminals, 22 test modes can be set, and if the integrated circuit has one test terminal, 2n test modes can be set. For example, as shown in No. 11, the three test terminals T1
．． T2. For watch LSI10 having T3, 2
328 test modes can be performed. In this case, terminal T
I, T2. T3 (1) Signal level 1.5V (7)
If the signal level is 0 and the signal level is 0 and the outside is shown as the LOIll level, then as shown in Table 1, the terminals T, , T2
, i” are all at the “Higl+” level, the mode is “64Hz signal fast forward” and the terminal T1 is “
When the terminals T2 and T3 are at the “HighI+” level at the “Lou+” level, the mode is “1 second signal fast forward” and the terminal Tl
1T'l is at "High" level and terminal T2 is g L o
When it is at the IIIT level, the mode is "1 minute signal fast forward".Hereinafter, terminals T, , T,.

The modes shown in Table 1 are set depending on the signal levels of signals 1 and 3.

Table 1 H=1.50V, L=0. OOV In this way, the test mode is determined depending on the number of test terminals. However, as integrated circuits become larger and more highly integrated, the number of test failure states increases and various test modes are required. Since the number of test terminals is limited due to dimensional constraints, there is a limit to the method of increasing the number of test modes by increasing the number of test terminals.

The present invention has been made in view of the above circumstances, and its purpose is to: 1) reduce the number of test terminals by providing a conversion circuit for predetermined bits for each test terminal; It is an object of the present invention to provide an integrated circuit capable of executing a large number of test modes without increasing the number of test modes.

A conversion circuit is connected between the nose-chestnut test terminal and the logic circuit, and a digital signal corresponding to a predetermined test mode is converted to the logic circuit according to the level of the analog voltage applied to the test terminal. By manually inputting a signal to one test terminal, multiple types of test modes can be executed.

Example An embodiment of the present invention will be described below.

In FIG. 2, reference numeral 100 denotes a watch LSI, and this watch LSI 100 is provided with three test terminals T, , T, , T3, like the above-mentioned conventional watch LSI.

This watch LSI 100 is equipped with an A-1) conversion circuit, a test terminal T1 is connected to the analog input terminal 1a of the A-D conversion circuit 1, and a test terminal T1 is connected to the analog input terminal 2a of the A-D conversion circuit 2. The terminal T2 is connected, and the test terminal 1-3 is connected to the analog input terminal 3a of the A-D conversion circuit 3.

Digital output terminal 1b of the A/D conversion circuit 1.

1c and 1d are test terminals Tl of the logic circuit 100a.
l l i'' l 211' l : l are connected to the test terminal T2 of the logic circuit 100a, and the digital output terminals 2b, 2c, 2d of the A-D conversion circuit 2 are connected to the test terminal T2 of the logic circuit 100a.
11T22+T2:l, respectively, and the digital output terminals 3b, 3ct 3d of the A-D conversion circuit 3 are respectively connected to the test terminal T311T321T33 of the logic circuit HB)a.

By applying voltage signals of various predetermined levels to the test terminals r and +l, digital signals corresponding to these voltage levels are output to the digital output terminals 11+ and l' of the A-D conversion circuit 1. c and ld, and this signal is input to the logic circuit 100a via the test terminal T l l l T + 21 T l :l. in this case,
Since the A/D converter circuit 1 has a 3-bit digital output, it converts 23-8 analog inputs into digital signals and outputs them. Table 2 shows the digital output of the A-D converter circuit 1 according to the analog input at the test terminal T1 and the meaning of the test mode.

The voltage level of test terminal T1 is 1.50V.
-Digital output of D conversion circuit 1 is terminal 11), 1
．． c and ld are all at the "High" level, and the test terminal 1' of the logic 1 circuit 100a is
+ Tl3 are all at 1liHb" level, and the test mode other than this is "641 (z signal fast forward).When the voltage level of test terminal T1 is 1.20 to
~-1) Terminal 11) of conversion circuit 1 is at “Low” level,
Terminals 1c and ld are both at the ``Highb'' level, test terminal 1 is at the ``0111pa'' level, and test terminals T121 and TI3 are both at the ``Hibi 11'' level.
), the test mode is ``1 second signal fast forward''. below,
The analog input is input with digital signals corresponding to six levels from 1.00 V to 0.00 V, and each digital signal is turned on and the test mode is executed.

Table 2 H = 1.50V, L = 0.1) OV This second
The eight test modes shown in the table are the same as those shown in Table 1. Therefore, conventionally, three test terminals TI, T2, . Whereas T3 was required, in this embodiment, eight test modes can be executed using only one test terminal T. in the end,
By using a 111-bit digital output A-D conversion circuit, two test modes can be executed by inputting a signal to one test terminal. Then, as shown in FIG. 2, three test terminals T, , T2 . If an A-D conversion circuit is provided for each T3, 2 m +
Three test modes can be performed.

Generally, an m-bit A-D converter circuit is tested by n tests + n tests.
+.

By providing one for each terminal, two test modes can be executed.

End As explained above, in the present invention, an A-D conversion circuit is connected between a test terminal and a logic circuit, and a predetermined voltage is set according to the level of the analog voltage applied to the test terminal. It is now possible to input a digital signal corresponding to the test mode into one logic circuit.Multiple types of test modes can be executed by inputting a signal to one test terminal.
The result is that a large number of test modes can be executed without increasing the number of test terminals and therefore without being constrained by the external dimensions of the integrated circuit. Furthermore, when the degree of integration of integrated circuits increases and the number of required test modes increases, the number of bits of the digital output of the A/D converter circuit can be increased to easily meet the requirements.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a conventional example of an integrated circuit, and FIG. 2 is a diagram showing an embodiment of the present invention. 100...LSI, 'r, , T2. T,・
・・Test terminal, 1.2.3・A-D conversion circuit, 1 a
, 2at 3a - analog input terminal, lb, Ic,
ld, 2b, 2c. 2d, 3b, 3c, 3d...Digital output terminal, ~100a...Logic circuit. Figure 1

Claims (1)

[Claims] (1) In an integrated circuit having a test terminal for inputting a signal for executing a predetermined test mode when testing the integrated circuit, an A-D converter circuit is provided, and the above-mentioned terminal is provided on the analog input side of the A-D converter circuit. By connecting a test terminal, connecting a logic circuit related to the test to the digital output side of the A-D conversion circuit, and inputting voltage signals of multiple levels to the test terminal, An integrated circuit configured to execute a predetermined test mode.