JP2019060784A - Test mode setting circuit - Google Patents

Abstract

To allow setting of a test mode with an easy configuration instead of a precise configuration, and suppress increase of the number of terminals.SOLUTION: There is provided a test mode setting circuit which gives N number of test mode signals to an LSI to respond to several (N number of) different types of test modes to run a test to an LSI. The test mode setting circuit has an A/D converter 10 for converting an analog signal into a digital signal. The test mode setting circuit inputs an analog test mode signal to the A/D converter 10, creates N number of test mode signals based on the output digital signal.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a test mode setting circuit for testing an LSI.

  In recent years, as the scale of LSI increases, the circuit configuration becomes more complicated, and the required IP (Intellectual property core) tends to increase. Such a test of LSI requires a large number of test modes, and when the number of test modes is increased, a large number of test terminals are required, which leads to an increase in the size of the LSI.

  The conventional test mode setting circuit obtains 16 output signals from the decoder 100 as shown in the truth table of FIG. 2, for example, as shown in FIG. 1, in order to execute 16 types of test modes. For this purpose, a 4-bit input is required, and accordingly, test terminals TEST0 to TEST3 of the input signal are required. Also, in order to activate the decoder 100, a terminal TESTEN of the enable signal is required. Therefore, a total of five terminals are required, which may lead to an increase in size of the LSI.

  On the other hand, Patent Document 1 discloses a mode setting circuit that performs test mode control using an A / D converter. In this mode setting circuit, the power supply detection circuit 105 detects a voltage exceeding the user guaranteed potential, and the power supply voltage of the microcomputer is raised, and the power supply detection circuit 105 detects a voltage exceeding the user guaranteed potential and the test mode To make a transition to As a result, the number of mode dedicated pins is reduced without providing the user with a specific definition.

  Further, Patent Document 2 discloses setting of a test mode by an analog input signal. The invention of Patent Document 2 is to make it possible to set a desired test mode correctly even if there is an error in an analog signal for setting the test mode. Specifically, a plurality of test modes are set in accordance with the difference in rise time of the analog signal for setting the test mode.

  Further, Patent Document 3 discloses a test circuit which performs a test using an output of an A / D converter in an LSI provided with the A / D converter. That is, in the test mode, a predetermined digital signal is output from the test decode circuit 7, and the output of the A / D converter is applied to the ROM or RAM to perform digital signal processing, and the result is output terminal It is output from 4.

JP, 2007-155659, A JP, 2013-149026, A Japanese Patent Laid-Open No. 2002-5994

  In the test mode setting circuit of Patent Document 1, the power supply detection circuit 105 detects a voltage exceeding the user-guaranteed potential and validates the input signal (time) while shifting to the test mode. There is a problem that the control of (time) must be properly and properly performed during the transition to the above, and a relatively detailed control is required.

  Also, in the test mode setting circuit of Patent Document 2, the output of the A / D converter is given to the CPU so that the CPU performs necessary correction so that the desired test mode can be set correctly even if there is an error in the analog signal. There is a problem that processing and configuration are complicated.

  Furthermore, although the test circuit of Patent Document 3 uses the upper 3 bits of the output of the A / D converter for mode switching, it is also a circuit to be tested and must be highly accurate.

  The present invention has been made in view of the current state of the conventional test mode setting circuit as described above, and its object is to simplify the configuration and to set the test mode without providing a highly accurate configuration. It is an object of the present invention to provide a test mode setting circuit capable of suppressing an increase in the number of terminals.

  The test mode setting circuit according to the present invention is a test mode setting circuit that applies N test mode signals to the LSI corresponding to a plurality of types of test modes in order to test the LSI. An analog test mode signal input to the A / D conversion device, N test mode signals are generated based on the output digital signal, and provided to the LSI. Do.

  In the test mode setting circuit according to the present invention, the A / D conversion device receives a serial A / D conversion circuit which converts an analog signal into a digital signal and serially outputs the signal and an output of the serial A / D conversion circuit. And a shift register for outputting as a parallel signal, and a decoder for generating N test mode signals from an output signal of the shift register in addition to the A / D conversion device. Do.

  In the test mode setting circuit according to the present invention, the A / D conversion device includes a parallel A / D conversion circuit that converts an analog signal into a parallel digital signal and outputs the same, and an output signal of the parallel A / D conversion circuit. And a decoder for producing N test mode signals.

  The test mode setting circuit according to the present invention is characterized in that the upper predetermined bits of all the output bits of the circuit of the preceding stage of the decoder are inputted to the decoder.

  In the test mode setting circuit according to the present invention, all output bits of the circuit in the previous stage of the decoder are input to the decoder, and predetermined output signals obtained correspondingly are collectively input to the N logic operation circuits. It is characterized in that the output of the logic operation circuit is N test mode signals.

  In the test mode setting circuit according to the present invention, the serial A / D conversion circuit has an input terminal for inputting a plurality of analog signals, and a shift register is provided with a number corresponding to the number of the input terminals. It is characterized by

  A test mode setting circuit according to the present invention is characterized in that an input buffer of an LSI is used as the A / D converter.

  In the test mode setting circuit according to the present invention, the A / D conversion device includes a buffer for holding an input, and a logic circuit for converting the output of the buffer into a digital value, and the output of the buffer It is characterized in that N (N = 2) test mode signals are generated by the output of the logic circuit.

  The test mode setting circuit according to the present invention includes an input buffer of an LSI, an AD conversion circuit provided on the output side of the input buffer, and a logic circuit for creating a digital value based on the output of the AD conversion circuit. Is used as the A / D conversion device, and N test mode signals are generated from the output of the AD conversion circuit and the output of the logic circuit.

  In the test mode setting circuit according to the present invention, the test mode setting is performed only when the test mode is executed by making the operation power supply voltage of the LSI different from the operation power supply voltage of the test mode setting circuit including the A / D converter. A predetermined operating power supply voltage is applied to the circuit.

  The test mode setting circuit according to the present invention includes an A / D conversion device for converting an analog signal into a digital signal, and the analog test mode signal is input to the A / D conversion device, and N analog signals are output based on the output digital signal. The test mode signal is generated and given to the LSI, so the configuration is simple, and the A / D conversion device can be dedicated to test mode setting, so test mode setting is possible without having a high-precision structure. It is possible to suppress the increase in the number of terminals.

The block diagram which shows the structure of the conventional test mode setting circuit. FIG. 6 is a truth table of a decoder used in the test mode setting circuit of FIG. 1; FIG. 2 is a block diagram showing the configuration of a test mode setting circuit according to the first embodiment. FIG. 7 is a block diagram showing a configuration of a test mode setting circuit according to a second embodiment. FIG. 10 is a block diagram showing the configuration of a test mode setting circuit according to a third embodiment. FIG. 14 is a block diagram showing the configuration of a test mode setting circuit according to a fourth embodiment. FIG. 13 is a block diagram showing the configuration of a test mode setting circuit according to a fifth embodiment. The block diagram which shows the structure of an input buffer. FIG. 16 is a block diagram showing a configuration of a test mode setting circuit according to a sixth embodiment. FIG. 2 is a view showing the configuration of an LSI provided with a configuration for preventing malfunction.

  Hereinafter, an embodiment of a test mode setting circuit according to the present invention will be described with reference to the attached drawings. FIG. 3 shows the configuration of the first embodiment of the test mode setting circuit according to the present invention. In this test mode setting circuit, the A / D converter 10 includes a serial A / D converter circuit 11, a shift register 12, and a controller 13. The A / D conversion device 10 converts an analog signal into a digital signal, and the test mode setting circuit is provided with a decoder 18 in addition to the A / D conversion device 10 described above.

  The serial A / D conversion circuit 11 converts an analog signal input from the TEST0 terminal into a digital signal and serially outputs it. The shift register 12 receives an output signal from the serial A / D conversion circuit 11 and outputs it as a parallel signal. In the present embodiment, the shift register 12 outputs a 4-bit (Q [3: 0]) parallel signal.

  The controller 13 receives the enable signal from the TESTEN terminal and the system clock CLK, and provides control signals to the serial A / D conversion circuit 11 and the shift register 12. Specifically, the serial A / D conversion circuit 11 is put into operation by the CSB signal and the SDIN signal, and the shift register 12 is put into operation by the CSB signal. The output clock CLK0 is supplied as a clock of the serial A / D conversion circuit 11 and the shift register 12 to perform an operation.

  When four clocks are output under the control of the controller 13 described above, 4-bit output data from the serial A / D conversion circuit 11 is accumulated in the shift register 12. The controller 13 outputs the enable signal EN0 to the decoder 18, decodes the 4-bit parallel signal output from the shift register 12, and outputs up to 16 test mode signals. Up to 16 test mode signals can be applied to the circuit under test in the LSI. According to this configuration, the serial A / D conversion circuit 11 only needs to output 1 or 0 at each clock, so it does not have to have high resolution.

  In the first embodiment described above, the serial A / D conversion circuit 11 and the shift register 12 are used, but the serial A / D conversion circuit 11 is a parallel A / D conversion circuit, and the shift register 12 holds parallel data. The configuration may be replaced with a register. Even in this case, since the parallel A / D conversion circuit does not divert the LSI system, it does not have to be highly accurate.

  FIG. 4 shows the configuration of a test mode setting circuit according to the second embodiment. In this embodiment, the shift register 12A that receives the output signal of the serial A / D conversion circuit 11 is output as 6 bits (Q [5: 0]). The decoder 18 takes in the upper 4 bits in the output of the shift register 12A, decodes it, and outputs up to 16 test mode signals. In this embodiment, since the upper 4 bits of the 6-bit output are used, the A / D conversion circuit can be configured to rely on the low resolution side (upper bit side), and it is not a high precision resolution. It is good. Also in this embodiment, the serial A / D conversion circuit 11 may be a parallel A / D conversion circuit, and the shift register 12A may be replaced with a register for holding parallel data.

  FIG. 5 shows the configuration of a test mode setting circuit according to the third embodiment. In this embodiment, the serial A / D conversion circuit 11 and the shift register 12A shown in FIG. 4 are used, and the decoder 18A receives 6 bits (T [5: 0]) of the shift register 12A. The decoder 18A decodes the 6-bit input into 48 output signals. The three adjacent ones of the 48 output signals are applied to the OR gates 17-0 to 17-15. A total of 16 output signals can be obtained from the OR gates 17-0 to 17-15 and can be applied to the circuit under test in the LSI. In the present embodiment, the resolution is lowered at the output of the decoder 18A. Also in this embodiment, the serial A / D conversion circuit 11 may be a parallel A / D conversion circuit, and the shift register 12A may be replaced with a register for holding parallel data.

  FIG. 6 shows the configuration of a test mode setting circuit according to the fourth embodiment. In this embodiment, a serial A / D conversion circuit 11A having two analog signal input terminals is used. Analog signals are supplied to the two analog signal input terminals from the TEST0 terminal and the TEST1 terminal. The output of serial A / D conversion circuit 11A is applied to two shift registers 12B-1 and 12B-2.

  The controller 13A includes two enable terminals EN1O and EN2O, applies an enable signal from the enable terminal EN1O to the shift register 12B-1, and applies an enable signal from the enable terminal EN2O to the shift register 12B-2. When an enable signal from the enable terminal EN1O is active, an analog signal is applied to the TEST0 terminal. Also, when the enable signal from the enable terminal EN2O is active, an analog signal is supplied to the TEST1 terminal. The controller 13A supplies the output clock CLK0 as a clock of the shift registers 12B-1 and 12B-2 to perform an operation.

  The shift register 12B-1 that operates when the enable signal from the enable terminal EN1O is active, and the shift register 12B-2 that operates when the enable signal from the enable terminal EN2O is active are also three bits (Q [2: 0 ]] Parallel signal is output.

  The decoder 18B has 2 inputs, takes in the input of the lower 2 bits (D [1: 0]) by the upper 2 bits from the shift register 12B-1, and shifts the input of the upper 2 bits (D [3: 2]) The upper two bits from the register 12B-2 are fetched. The decoder 18B is a 4-bit input in total and can output up to 16 test mode signals.

  With the above configuration, since the serial A / D conversion circuit 11A has a low resolution of 3 bits and the upper 18 bits are taken in by the decoder 18B, the resolution can be further lowered. The serial A / D conversion circuit 11A of this embodiment may be replaced by a parallel A / D conversion circuit, and the shift registers 12B-1 and 12B-2 may be replaced by two parallel input registers.

  FIG. 7 shows the configuration of a test mode setting circuit according to the fifth embodiment. In this embodiment, the configuration of the second embodiment is basically adopted. However, the decoder 18A discards the upper 1 bit and the lower 1 bit in the 6-bit output (Q [5: 0]) of the shift register 12A, and inputs the central 4 bits among the 6 bits (D [3: 0]).

  In this configuration, it is not sufficient to operate the decoder 18 by outputting the enable signal EN0 from the controller 13 to the decoder 18 for fail safe reasons, so the NAND gate 21 and the OR gate 22 are used. The 4-bit signal input from the shift register 12A to the NAND gate 21 is input to the NAND gate 21. The output signal from the NAND gate 21 and the enable signal EN0 from the controller 13 are input to the OR gate 22. The output of gate 22 is applied to the enable terminal EN of decoder 18. This configuration can prevent a malfunction.

In this embodiment, the upper 1 bit and the lower 1 bit in the 6-bit output (Q [5: 0]) of the shift register 12A are discarded, and the center 4 bits among 6 bits are adopted, so the resolution is low. can do. Also in this embodiment, the serial A / D conversion circuit 11 may be a parallel A / D conversion circuit, and the shift register 12A may be replaced with a register for holding parallel data.

  FIG. 8 shows the configuration of the input buffer. In this input buffer, an A / D conversion device is created by the buffer 31 which holds an input, and the NAND gate 32 which is a logic circuit which makes the output of the buffer a modified digital value. The role of the input buffer 31 is that when a signal is directly taken into the LSI, the transistor inside the LSI prevents gate breakdown due to surge voltage or noise, etc. The input buffer 31 means a non-inverting buffer including a protection circuit. is there.

  An input signal is input to the buffer 31 from the input terminal A. The output of the buffer 31 is applied to one input of the NAND gate 32, and the signal PI is input to the other input of the NAND gate 32. This input buffer is a two-state output of "0" or "1". Therefore, in the case of adopting a 2-bit output as the A / D device 10 of each embodiment, this input buffer can be configured instead of the A / D device 10 as it is. That is, this embodiment is characterized in that the input buffer of the LSI is used as an A / D converter.

  An ADC (A / D conversion circuit) 33 is incorporated into the above input buffer to form a 3-bit A / D conversion circuit. FIG. 9 shows the main configuration of a test mode setting circuit according to the fifth embodiment. In this embodiment, a 2-bit output ADC 33 is connected to the output of the buffer 31. That is, for multi-leveling (four values in this embodiment), the input buffer of FIG. 8 incorporates an ADC. An enable signal EN is provided to the ADC 33 as a test mode setting circuit. An analog signal is input to the buffer 31 from the input terminal A.

  The clock of the ADC 33 is generated internally based on the enable signal EN, or externally supplied to the ADC 33 although not shown. The NAND gate 34 has three inputs and receives the two outputs of the ADC 33 and the signal PI when used as an input buffer. The output signals Z0 and Z1 of the ADC 33 and the output signal PO of the NAND gate 34 are applied to the decoder to provide a test mode setting signal. With this configuration, it is possible to realize a test mode setting circuit with an A / D conversion circuit with a low resolution of about 2 to 3 bits. The NAND 32 and the NAND 34 can simply test whether the input of the IO buffer normally functions by connecting the output PO to the input PI of the next IO buffer and forming a tree shape on all the IO terminals of the LSI. Since the ADC 33 samples the input signal, the ADC 33 in FIG. 9 has a built-in oscillator of the sampling clock, and also has a function of holding the output of the ADC 33 (eg, the enable signal EN updates on and keeps off) Also has.

  That is, in this embodiment, the configuration includes an input buffer of an LSI, an AD conversion circuit provided on the output side of the input buffer, and a logic circuit for creating a digital value based on the output of the AD conversion circuit. It is used as an A / D converter. Then, N test mode signals are generated by the output of the AD conversion circuit and the output of the logic circuit.

  FIG. 10 shows a configuration that does not cause the test mode setting circuit according to each of the embodiments described above to malfunction. A test mode setting circuit (including an A / D conversion device 10 and a decoder) 40 according to each embodiment and a test target circuit 50 in the LSI are included in the LSI 60.

  The operating power supply voltage VL of the test target circuit 50 in the LSI and the operating power supply voltage VT of the test mode setting circuit 40 are different from each other, and only when the test mode is executed. give. Generally, it is assumed that VL <VT. Thus, the test mode setting operation is performed only when the operation power supply voltage VT is applied to the A / D conversion device, and erroneous transition to the test mode is not caused by the normal power supply voltage.

10 A / D Converter 11, 11A A / D Converter 12, 12A, 12B Shift Register 13, 13A Controller 18, 18A, 18B Decoder 40 Test Mode Setting Circuit 50 Test Target Circuit 60 LSI

Claims (10)

In order to test an LSI, in a test mode setting circuit that provides N test mode signals to the LSI corresponding to a plurality of types of test modes,
An A / D converter for converting an analog signal to a digital signal;
A test mode setting circuit characterized in that an analog test mode signal is input to the A / D conversion device, N test mode signals are generated based on the output digital signal, and are supplied to an LSI. The A / D conversion device
A serial A / D conversion circuit which converts an analog signal into a digital signal and serially outputs it;
A shift register which receives the output of the serial A / D conversion circuit and outputs it as a parallel signal;
Is equipped with
2. The test mode setting circuit according to claim 1, further comprising a decoder for generating N test mode signals from output signals of the shift register, in addition to the A / D conversion device. The A / D conversion device
A parallel A / D conversion circuit which converts an analog signal into a parallel digital signal and outputs it;
The test mode setting circuit according to claim 1, further comprising: a decoder for generating N test mode signals from output signals of the parallel A / D conversion circuit.   4. The test mode setting circuit according to claim 2, wherein upper predetermined bits of all the output bits of the circuit of the preceding stage of the decoder are input to the decoder.   All output bits of the circuit in the previous stage of the decoder are input to the decoder, and predetermined output signals obtained correspondingly are collectively input to the N logic operation circuits, and the outputs of the logic operation circuits are N tests 4. The test mode setting circuit according to claim 2, wherein a mode signal is used. The serial A / D conversion circuit has an input terminal for inputting a plurality of analog signals,
3. The test mode setting circuit according to claim 2, wherein a number corresponding to the number of the input terminals is provided in the shift register.   7. The test mode setting circuit according to claim 6, wherein upper predetermined bits of all the output bits of the circuit of the preceding stage of the decoder are input to the decoder.   The test mode setting circuit according to any one of claims 1 to 7, wherein an input buffer of an LSI is used as the A / D converter. LSI input buffer,
An AD converter circuit provided on the output side of the input buffer;
And a logic circuit for creating a digital value based on the output of the AD conversion circuit, used as the A / D conversion device.
The test mode setting circuit according to any one of claims 1 to 7, wherein N test mode signals are generated by the output of the AD conversion circuit and the output of the logic circuit.   The operation power supply voltage of the LSI and the operation power supply voltage of a test mode setting circuit including the A / D conversion device are made different, and a predetermined operation power supply voltage is applied to the test mode setting circuit only when the test mode is executed. The test mode setting circuit according to any one of claims 1 to 9, characterized by:

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